ADSP-2183KCA-210 ,DSP MicrocomputerOVERVIEW• Receive and transmit data through the two serial ports The ADSP-2183 instruction set prov ..
ADSP2183KCA-210 ,DSP Microcomputerfeatures:that the output of any unit may be the input of any unit on the• 35.7 MHz ADSP-2189M next ..
ADSP-2183KST-115 ,DSP MicrocomputeraDSP MicrocomputerADSP-2183FUNCTIONAL BLOCK DIAGRAM
ADSP-2183-KST-133 ,DSP MicrocomputerOVERVIEW• Receive and transmit data through the two serial ports The ADSP-2183 instruction set prov ..
ADSP-2183KST-133 ,DSP MicrocomputerGENERAL DESCRIPTION16K Words On-Chip Program Memory RAMThe ADSP-2183 is a single-chip microcomputer ..
ADSP-2183KST-160 ,DSP Microcomputerapplications.and Data StorageThe ADSP-2183 combines the ADSP-2100 family base architec-Independent ..
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AM2502PC ,EIGHT BIT / TWELVEFEATURES
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AM2503PC ,EIGHT BIT / TWELVE[INTEKHIL
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ADSP-2183BST-133-ADSP-2183BST-160-ADSP-2183KCA-210-ADSP2183KCA-210-ADSP-2183KST-115-ADSP-2183-KST-133-ADSP-2183KST-133-ADSP-2183KST-160-ADSP-2183-KST-210-ADSP-2183KST-210-ADSP2183KST-210
DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAMDSP Microcomputer
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time from 26.32 MHz Crystal
@ 3.3 Volts
52 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 300 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead LQFP, 144-Ball Mini-BGA
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final SystemsICE-Port is a trademark of Analog Devices, Inc.
GENERAL DESCRIPTIONThe ADSP-2183 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2183 combines the ADSP-2100 family base architec-
ture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.
The ADSP-2183 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equipment.
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball
Mini-BGA packages.
In addition, the ADSP-2183 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2183 operates with a 19 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2183’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2183 can:Generate the next program addressFetch the next instructionPerform one or two data movesUpdate one or two data address pointersPerform a computational operation
ADSP-2183This takes place while the processor continues to:Receive and transmit data through the two serial portsReceive and/or transmit data through the internal DMA portReceive and/or transmit data through the byte DMA portDecrement timer
Development SystemThe ADSP-2100 Family Development Software, a complete
set of tools for software and hardware system development,
supports the ADSP-2183. The assembler has an algebraic syntax
that is easy to program and debug. The linker combines object
files into an executable file. The simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment.
The EZ-KIT Lite is a hardware/software kit offering a com-
plete development environment for the ADSP-21xx family:
an ADSP-2189M evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
The ADSP-2189M evaluation board is a low-cost, easy to use
hardware platform on which you can quickly get started with
your DSP software design. The EZ-KIT Lite include the
following features:35.7 MHz ADSP-2189MFull 16-bit Stereo Audio I/O with AD73322 CODECRS-232 InterfaceEZ-ICE Connector for Emulator ControlDSP Demo ProgramsEvaluation Suite of VisualDSP
The ADSP-218x EZ-ICE® Emulator aids in the hardware debug-
ging of ADSP-218x systems. The ADSP-218x integrates on-chip
emulation support with a 14-pin ICE-Port interface. This inter-
face provides a simpler target board connection requiring fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICEs. The ADSP-218x device need not be removed
from the target system when using the EZ-ICE, nor are any
adapters needed. Due to the small footprint of the EZ-ICE
connector, emulation can be supported in final board designs.
The EZ-ICE performs a full range of functions, including:In-target operationUp to 20 breakpointsSingle-step or full-speed operationRegisters and memory values can be examined and alteredPC upload and download functionsInstruction-level emulation of program booting and executionComplete assembly and disassembly of instructionsC source-level debugging
(See Designing An EZ-ICE-Compatible Target System section
of this data sheet for exact specifications of the EZ-ICE target
board connector.)
Additional InformationThis data sheet provides a general overview of ADSP-2183
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual, Third Edition. For more information about the
development tools, refer to the ADSP-2100 Family Development
Tools Data Sheet.
ARCHITECTURE OVERVIEWThe ADSP-2183 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-2183 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Figure 1 is an overall block diagram of the ADSP-2183. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and arith-
metic shifts, normalization, denormalization and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
The ADSP-21xx family DSPs contain a shadow register that is
useful for single cycle context switching of the processor.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2183 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
Efficient data transfer is achieved with the use of five internal
buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2183 to fetch two operands in a single cycle,
one from program memory and one from data memory. The
ADSP-2183 can fetch an operand from program memory and
In addition to the address and data bus for external memory
connection, the ADSP-2183 has a 16-bit Internal DMA port
(IDMA port) for connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
The byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with pro-
grammable wait state generation. External devices can gain
control of external buses with bus request/grant signals (BR,
BGH and BG). One execution mode (Go Mode) allows the
ADSP-2183 to continue running from on-chip memory. Normal
execution mode requires the processor to halt while buses are
granted.
The ADSP-2183 can respond to thirteen possible interrupts,
eleven of which are accessible at any given time. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal.
The two serial ports provide a complete synchronous serial inter-
face with optional companding in hardware and a wide variety of
framed or frameless data transmit and receive modes of operation.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The ADSP-2183 provides up to 13 general-purpose flag pins.
The data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, eight
flags are programmable as inputs or outputs and three flags are
always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-2183 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-2183
SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, for further details.SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.SPORTs can use an external serial clock or generate their
own serial clock internally.SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals, internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
ADSP-2183SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
Pin DescriptionsThe ADSP-2183 is available in a 128-lead LQFP package, and
Mini-BGA.
PIN FUNCTION DESCRIPTIONS*These ADSP-2183 pins must be connected only to the EZ-ICE connector in
the target system. These pins have no function except during emulation, and
do not require pull-up or pull-down resistors.
InterruptsThe interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-2183 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1 and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN and
FLAG_OUT, for a total of six external interrupts. The ADSP-
2183 also supports internal interrupts from the timer, the byte
DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized and
individually maskable (except power-down and reset). The
IRQ2, IRQ0 and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge sensitive. The priorities and vector
addresses of all interrupts are shown in Table I.
Table I.Interrupt Priority and Interrupt Vector AddressesSPORT1 Receive or IRQ0
Interrupt routines can either be nested, with higher priority
interrupts taking precedence, or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2183 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are
twelve levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATIONThe ADSP-2183 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:Power-DownIdleSlow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-DownThe ADSP-2183 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. Refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter for detailed
information about the power-down feature.Quick recovery from power-down. The processor begins
executing instructions in as few as 300 CLKIN cycles.Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 300 CLKIN cycle recovery.Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 300 CLKIN
cycle start-up.Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
•The RESET pin also can be used to terminate
power-down.Power-down acknowledge pin indicates when the
processor has entered power-down.
IdleWhen the ADSP-2183 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.
Slow IdleThe IDLE instruction is enhanced on the ADSP-2183 to
let the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock frequency,
a programmable fraction of the normal clock rate, is speci-
fied by a selectable divisor given in the IDLE instruction.
The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.
ADSP-2183When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock, and thus its response time, to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2183 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems with an exter-
nally generated serial clock (SCLK), the serial clock rate may be
faster than the processor’s reduced internal clock rate. Under
these conditions, interrupts must not be generated at a faster
rate than can be serviced, due to the additional time the processor
takes to come out of the idle state (a maximum of n processor
cycles).
SYSTEM INTERFACEFigure 2 shows a typical basic system configuration with the
ADSP-2183, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2183 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
Figure 2.ADSP-2183 Basic System Configuration
Clock SignalsThe ADSP-2183 can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2183 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2183 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
Figure 3.External Crystal Connections
ResetThe RESET signal initiates a master reset of the ADSP-2183.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
Table II.This organization provides for two external 8K overlay segments
using only the normal 14 address bits. This allows for simple
program overlays using one of the two external segments in
place of the on-chip memory. Care must be taken in using this
overlay space because the processor core (i.e., the sequencer)
does not take the PMOVLAY register value into account. For
example, if a loop operation were occurring on one of the exter-
nal overlays, and the program changes to another external over-
lay or internal memory, an incorrect loop operation could occur.
In addition, care must be taken in interrupt service routines as
the overlay registers are not automatically saved and restored on
the processor mode stack.
For ADSP-2100 Family compatibility, MMAP = 1 is allowed.
In this mode, booting is disabled and overlay memory is dis-
abled (PMOVLAY must be 0). Figure 5 shows the memory map
in this configuration.
Figure 5.Program Memory (MMAP = 1)
Data MemoryThe ADSP-2183 has 16,352 16-bit words of internal data
memory. In addition, the ADSP-2183 allows the use of 8K
external memory overlays. Figure 6 shows the organization of
the data memory.
Memory ArchitectureThe ADSP-2183 provides a variety of memory and peripheral
interface options. The key functional groups are Program
Memory, Data Memory, Byte Memory and I/O.
Program Memory is a 24-bit-wide space for storing bothinstruction opcodes and data. The ADSP-2183 has 16K words
of Program Memory RAM on chip and the capability of access-
ing up to two 8K external memory overlay spaces using the
external data bus. Both an instruction opcode and a data value
can be read from on-chip program memory in a single cycle.
Data Memory is a 16-bit-wide space used for the storage ofdata variables and for memory-mapped control registers. The
ADSP-2183 has 16K words on Data Memory RAM on chip,
consisting of 16,352 user-accessible locations and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus.
Byte Memory provides access to an 8-bit-wide memory spacethrough the Byte DMA (BDMA) port. The Byte Memory inter-
face provides access to 4 MBytes of memory by utilizing eight
data lines as additional address lines. This gives the BDMA Port
an effective 22-bit address range. On power-up, the DSP can
automatically load bootstrap code from byte memory.
I/O Space allows access to 2048 locations of 16-bit-wide data.It is intended to be used to communicate with parallel periph-
eral devices such as data converters and external registers or
latches.
Program MemoryThe ADSP-2183 contains a 16K × 24 on-chip program RAM.
The on-chip program memory is designed to allow up to two
accesses each cycle so that all operations can complete in a
single cycle. In addition, the ADSP-2183 allows the use of 8K
external memory overlays.
The program memory space organization is controlled by the
MMAP pin and the PMOVLAY register. Normally, the ADSP-
2183 is configured with MMAP = 0 and program memory orga-
nized as shown in Figure 4.
Figure 4.Program Memory (MMAP = 0)
There are 16K words of memory accessible internally when the
PMOVLAY register is set to 0. When PMOVLAY is set to
something other than 0, external accesses occur at addresses
0x2000 through 0x3FFF. The external address is generated as
shown in Table II.
ADSP-2183The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits, except the BMS
bit, default to 1 at reset.
Byte MemoryThe byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The byte memory space
consists of 256 pages, each of which is 16K × 8.
The byte memory space on the ADSP-2183 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
Byte Memory DMA (BDMA)The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space,
while the processor is operating normally and steals only one
DSP cycle per 8-, 16- or 24-bit word transferred.
The BDMA circuit supports four different data formats which
are selected by the BTYPE register field. The appropriate num-
ber of 8-bit accesses are done from the byte memory space to
build the word size selected. Table V shows the data formats
supported by the BDMA circuit.
Table V.Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
The source or destination of a BDMA transfer will always be
There are 16,352 words of memory accessible internally when
the DMOVLAY register is set to 0. When DMOVLAY is set to
something other than 0, external accesses occur at addresses
0x0000 through 0x1FFF. The external address is generated as
shown in Table III.
Table III.This organization allows for two external 8K overlays using only
the normal 14 address bits.
All internal accesses complete in one cycle. Accesses to external
memory are timed using the wait states specified by the DWAIT
register.
I/O SpaceThe ADSP-2183 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals or to bus interface ASIC data registers.
I/O space supports 2048 locations. The lower eleven bits of the
external address bus are used; the upper 3 bits are undefined.
Two instructions were added to the core ADSP-2100 Family
instruction set to read from and write to I/O memory space.
The I/O space also has four dedicated 3-bit wait state regis-
ters, IOWAIT0-3, which specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table IV.
Table IV.
Composite Memory Select (CMS)The ADSP-2183 has a programmable memory select signal that
is useful for generating memory select signals for memories
mapped to more than one space. The CMS signal is generated
to have the same timing as each of the individual memory select
signals (PMS, DMS, BMS, IOMS) but can combine their
functionality.
When set, each bit in the CMSSEL register causes the CMS
signal to be asserted when the selected memory select is as-
serted. For example, to use a 32K word memory to act as both
program and data memory, set the PMS and DMS bits in the
CMSSEL register and use the CMS pin to drive the chip
select of the memory; use either DMS or PMS as the additional
Table VI.Boot Summary Table
BDMA BootingWhen the BMODE and MMAP pins specify BDMA booting
(MMAP = 0, BMODE = 0), the ADSP-2183 initiates a BDMA
boot sequence when reset is released. The BDMA interface is
set up during reset to the following defaults when BDMA boot-
ing is specified: the BDIR, BMPAGE, BIAD and BEAD regis-
ters are set to 0, the BTYPE register is set to 0 to specify
program memory 24 bit words, and the BWCOUNT register is
set to 32. This causes 32 words of on-chip program memory to
be loaded from byte memory. These 32 words are used to set up
the BDMA to load in the remaining program code. The BCR
bit is also set to 1, which causes program execution to be held
off until all 32 words are loaded into on-chip program memory.
Execution then begins at address 0.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface.
IDMA BootingThe ADSP-2183 can also boot programs through its Internal
DMA port. If BMODE = 1 and MMAP = 0, the ADSP-2183
boots from the IDMA port. IDMA feature can load as much on-
chip memory as desired. Program execution is held off until on-
chip program memory location 0 is written to.
The ADSP-2100 Family Development Software (Revision 5.02
and later) can generate IDMA compatible boot code.
Bus Request and Bus GrantThe ADSP-2183 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-2183 is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,asserting the bus grant (BG) signal, and
When the BWCOUNT register is written with a nonzero value
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
a destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The BDMA Context Reset bit (BCR) controls whether the
processor is held off while the BDMA accesses are occurring.
Setting the BCR bit to 0 allows the processor to continue opera-
tions. Setting the BCR bit to 1 causes the processor to stop
execution while the BDMA accesses are occurring, to clear the
context of the processor and start execution at address 0 when
the BDMA accesses have completed.
Internal Memory DMA Port (IDMA Port)The IDMA Port provides an efficient means of communication
between a host system and the ADSP-2183. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
ADSP-2183 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This in-
creases throughput as the address does not have to be sent for
each memory access.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a 14-
bit address and 1-bit destination type can be driven onto the bus
by an external device. The address specifies an on-chip memory
location; the destination type specifies whether it is a DM or
PM access. The falling edge of the address latch signal latches
this value into the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2183’s on-chip memory. Asserting the
select line (IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2183 that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
one additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation.
Bootstrap Loading (Booting)The ADSP-2183 has two mechanisms to allow automatic load-
ing of the on-chip program memory after reset. The method for
booting after reset is controlled by the MMAP and BMODE
pins as shown in Table VI.
ADSP-2183If Go Mode is enabled, the ADSP-2183 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the ADSP-2183 is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes. The instruction
does not need to be completed when the bus is granted. If a
single instruction requires two external memory accesses, the
bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The BGH pin is asserted when the ADSP-2183 is ready to
execute an instruction, but is stopped because the external bus
is already granted to another device. The other device can re-
lease the bus by deasserting bus request. Once the bus is re-
leased, the ADSP-2183 deasserts BG and BGH and executes
the external memory access.
Flag I/O PinsThe ADSP-2183 has eight general purpose programmable in-
put/output flag pins. They are controlled by two memory
mapped registers. The PFTYPE register determines the direc-
tion, 1 = output and 0 = input. The PFDATA register is used to
read and write the values on the pins. Data being read from a
pin configured as an input is synchronized to the ADSP-2183’s
clock. Bits that are programmed as outputs will read the value
being output. The PF pins default to input during reset.
In addition to the programmable flags, the ADSP-2183 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1 and FL2.
FL0-FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.
INSTRUCTION SET DESCRIPTIONThe ADSP-2183 assembly language instruction set has an
algebraic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the ADSP-
2183’s interrupt vector and reset vector map.Sixteen condition codes are available. For conditional jump,
call, return or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEMThe ADSP-2183 has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
The ICE-Port interface consists of the following ADSP-2183 pins:
EBREBGERESET
EMSEINTECLK
ELINELOUTEE
These ADSP-2183 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-
down resistors. The traces for these signals between the ADSP-
2183 and the connector must be kept as short as possible, no
longer than three inches.
The following pins are also used by the EZ-ICE:BG
RESETGND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2183 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
Target Board Connector for EZ-ICE ProbeThe EZ-ICE connector (a standard pin strip header) is shown
in Figure 7. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
Figure 7.Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie, and Samtec.
Target Memory InterfaceFor your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines
listed below.
PM, DM, BM, IOM and CMDesign your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the ADSP-2183(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected
when the EZ-ICE is being used. The pull-up resistors are nec-
essary because there are no internal pull-ups to guarantee their
state during prolonged three-state conditions resulting from
typical EZ-ICE debugging sessions. These resistors may be
removed at your option when the EZ-ICE is not being used.
Target System Interface SignalsWhen the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced
by the EZ-ICE board:EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.EZ-ICE emulation ignores RESET and BR when single-
stepping.EZ-ICE emulation ignores RESET and BR when in Emula-
tor Space (DSP halted).EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
Target Architecture FileThe EZ-ICE software lets you load your program in its linked
(executable) form. The EZ-ICE PC program can not load
sections of your executable located in boot pages (by the
linker). With the exception of boot page 0 (loaded into PM
RAM), all sections of your executable mapped into boot pages
are not loaded.
Write your target architecture file to indicate that only PM
RAM is available for program storage, when using the EZ-ICE
software’s loading feature. Data can be loaded to PM RAM or
DM RAM.
ADSP-2183–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSVIL
VOL
IIH
IIL
IOZH
IOZL
IDD
IDD
NOTESBidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7.0 V on BR, CLKIN Active (to force three-state condition).Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.Current reflects device operating with no output loads.VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% aretype 2 and type 6, and 20% are idle instructions.
TIMING PARAMETERS
GENERAL NOTESUse the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a
device connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.
MEMORY TIMING SPECIFICATIONSThe table below shows common memory device specifications
and the corresponding ADSP-2183 timing parameters, for your
convenience.
xMS = PMS, DMS, BMS, CMS, IOMS.
FREQUENCY DEPENDENCY FOR TIMING
SPECIFICATIONStCK is defined as 0.5tCKI. The ADSP-2183 uses an input clock
with a frequency equal to half the instruction rate: a 16.67 MHz
input clock (which is equivalent to 60 ns) yields a 30 ns proces-
sor cycle (equivalent to 33 MHz). tCK values within the range of
0.5tCKI period should be substituted for all relevant timing pa-
rameters to obtain the specification value.
Example: tCKH = 0.5tCK – 7 ns = 0.5 (34.7 ns) – 7 ns = 10.35 ns
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. These are stress ratings only; functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ADSP-2183tCKIL
tCKIH
Switching Characteristics:
tCKL
Control SignalsTiming Requirement:
NOTEApplies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Figure 8.Clock Signals
tIFH
NOTESIf IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to Interrupt Controller Operation in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced.IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQE.PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7.Flag outputs = PFx, FL0, FL1, FL2, Flag_out4.
NOTES
xMS = PMS, DMS, CMS, IOMS, BMS.BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on
the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships.BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
Figure 10.Bus Request–Bus Grant
ADSP-2183tAA
tRDH
Switching Characteristics:
tRP
tASR
w = wait states × tCK.
xMS = PMS, DMS, CMS, IOMS, BMS.
Figure 11.Memory Read
