ADSP-2171KST-133 ,DSP Microcomputerapplications. The• perform a computational operationADSP-2171 and ADSP-2172 are designed for 5.0 V ..
ADSP-2173 ,16-bit, 20 MIPS, 3.3v, 2 serial ports, host portOVERVIEWPROM Splitter generates PROM programmer compatible files. Figure 1 is an overall block diag ..
ADSP-2173BST-80 ,DSP MicrocomputerFEATURES30 ns Instruction Cycle Time (33 MIPS) fromPOWERDOWN16.67 MHz Crystal at 5.0 V PROGRAMMEMOR ..
ADSP-2178-780244 ,GSM Baseband Processing ChipsetcharacteristicsThe BBC receives data at 270 kb/s. The on-chip lookup-tableand timing information.RO ..
ADSP-2181 ,16-bit, 40 MIPS, 5v, 2 Serial Ports, Host Port, 80 KB RAMapplications.and Data StorageIndependent ALU, Multiplier/Accumulator, and BarrelThe ADSP-2181 combi ..
ADSP-2181BS133 ,DSP Microcomputerfeatures:that the output of any unit may be the input of any unit on the• 33 MHz ADSP-2181next cycl ..
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-2171BST-133-ADSP-2171KS133-ADSP-2171KS-133-ADSP2171KS-133-ADSP-2171KST-133-ADSP-2173BST-80
DSP Microcomputer
FUNCTIONAL BLOCK DIAGRAMREV.A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
DSP Microcomputer
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipula-
tion Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP-
2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTIONThe ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-
tions. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
ADSP-2171/ADSP-2172/ADSP-2173
Development SystemThe ADSP-2100 Family Development Software, a complete settoolsforsoftwareandhardwaresystem development, supports
the ADSP-217x. The System Builder provides a high-level
method for defining the architecture of systems under develop-
ment. TheAssemblerhasanalgebraicsyntaxthatiseasyto
program and debug. The Linker combines object files into
an executable file. The Simulator provides an interactive
instruction-level simulation with a reconfigurable user interface
to display different portions of the hardware environment. A
PROM Splitter generates PROM programmer compatible files.
The C Compiler, based on the Free Software Foundation’s
GNU C Compiler, generates ADSP-217x assembly source
code. The Runtime Library includes over 100 ANSI-standard
mathematical and DSP-specific functions.
EZ-Tools, low cost, easy-to-use hardware tools, also support the
ADSP-217x.
The ADSP-217x EZ-ICE® Emulator aids in the hardware de-
bugging of ADSP-217x systems. The emulator consists of hard-
ware, host computer resident software, the emulator probe, and
the pin adaptor. The emulator performs a full range of emula-
tion functions including stand-alone operation or operation in
the target, setting up to 20 breakpoints, single-step or full-speed
operation in the target, examining and altering registers and
memory values, and PC upload/download functions. If you plan
to use the emulator, you should consider the emulator’s restric-
tions (differences between emulator and processor operation).
The EZ-LAB® Evaluation Board is a PC plug-in card, but it can
operate in stand-alone mode. The evaluation board/system de-
velopment board executes EPROM-based or downloaded pro-
grams. Modular Analog Front End daughter cards with different
codecs will be made available.
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
Additional InformationThis data sheet provides a general overview of ADSP-217x
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the Development
System and ADSP-217x programmer’s reference information,
refer to the ADSP-2100 Family Assembler Tools & Simulator
Manual.
ARCHITECTURE OVERVIEWFigure 1 is an overall block diagram of the ADSP-217x. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with
40 bits of accumulation. The shifter performs logical and
arithmetic shifts, normalization, denormalization, and derive
exponent operations. The shifter can be used to efficiently
implement numeric format control including multiword and
block floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be the input of any unit
on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-217x executes looped code
with zero overhead; no explicit jump instructions are required to
maintain the loop.
Figure 1.ADSP-217x Block Diagram
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and pro-
gram memory). Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Efficient data transfer is achieved with the use of five internal
buses.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus.
Program memory can store both instructions and data, permit-
ting the ADSP-217x to fetch two operands in a single cycle, one
from program memory and one from data memory. The ADSP-
217x can fetch an operand from on-chip program memory and
the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of external buses with bus
request/grant signals (BR and BG). One execution mode (Go
Mode) allows the ADSP-217x to continue running from inter-
nal memory. Normal execution mode requires the processor to
halt while buses are granted.
In addition to the address and data bus for external memory
connection, the ADSP-217x has a configurable 8- or 16-bit
Host Interface Port (HIP) for easy connection to a host proces-
sor. The HIP is made up of 16 data/address pins and 11 control
pins. The HIP is extremely flexible and provides a simple inter-
face to a variety of host processors. For example, the Motorola
68000 series, the Intel 80C51 series and the Analog Devices’
ADSP-2101 can be easily connected to the HIP. The host pro-
cessor can initialize the ASDP-217x’s on-chip memory through
the HIP.
The ADSP-217x can respond to eleven interrupts. There can be
up to three external interrupts, configured as edge or level sensi-
tive, and eight internal interrupts generated by the Timer, the
Serial Ports (“SPORTs”), the HIP, the powerdown circuitry,
and software. There is also a master RESET signal.
The two serial ports provide a complete synchronous serial in-
terface with optional companding in hardware and a wide vari-
ety of framed or frameless data transmit and receive modes of
operation. Each port can generate an internal programmable
serial clock or accept an external serial clock.
Boot circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
seven wait states are automatically generated. This allows, for
example, a 30 ns ADSP-217x to use an external 200 ns
EPROM as boot memory. Multiple programs can be selected
and loaded from the EPROM with no additional hardware. The
on-chip program memory can also be initialized through the
HIP.
The ADSP-217x features three general-purpose flag outputs
whose states can be simultaneously changed through software.
You can use these outputs to signal an event to an external
device. In addition, the data input and output pins on SPORT1
can be alternatively configured as an input flag and an output
flag.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycles, where n-l is a scaling value stored in an 8-bit regis-
ter (TSCALE). When the value of the count register reaches
zero, an interrupt is generated and the count register is reloaded
from a 16-bit period register (TPERIOD).
The ADSP-217x instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. The ADSP-217x assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
Serial PortsThe ADSP-217x incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
Here is a brief list of the capabilities of the ADSP-217x
SPORTs. Refer to the ADSP-2100 Family User’s Manual for
further details.
• SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
• SPORTs can use an external serial clock or generate their own
serial clock internally.
• SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
• SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and μ-law companding according
to CCITT recommendation G.711.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
• SPORT0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
• SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
ADSP-2171/ADSP-2172/ADSP-2173
Pin DescriptionThe ADSP-217x is available in 128-lead TQFP and 128-lead
PQFP packages. Table I contains the pin descriptions.
Table I.ADSP-217x Pin List
Pin#
GroupofInput/
NamePinsOutputFunctionAddress14OAddress output for program,
dataandbootmemory spaces
Data24I/OData I/O pins for program
and data memories. Input
only for boot memory space,
with two MSBs used as boot
space addresses.
RESET1IProcessor reset input
IRQ21IExternal interrupt request #21IExternal bus request input1OExternal bus grant output
BGH1OExternal bus grant hang output
PMS1OExternal program memory select
DMS1OExternal data memory select
BMS1OBoot memory select1OExternal memory read enable1OExternal memory write enable
MMAP1IMemory map select
CLKIN,
XTAL2IExternal clock or quartz crystal
input
CLKOUT1OProcessor clock output
HSEL1IHIP select input
HACK1OHIP acknowledge output
HSIZE18/16 bit host select input
0 = 16-bit; 1 = 8-bit
BMODE1IBoot mode select input
0 = EPROM/data bus; 1 = HIP
HMD01IBus strobe select input
0 = RD, WR; 1 = RW, DS
HMD11IHIP address/data mode select
input 0 = separate; 1 =
multiplexed
HRD/HRW1IHIP read strobe/read/write
select input
HWR/HDS1IHIP write strobe/host data
strobe select input
HD15–0/
HAD15-016I/OHIP data/data and address
HA2/ALE1IHost address 2/Address latch
enable input
HA1–0/
Unused2IHost addresses 1 and 0 inputs
SPORT05I/OSerial port 0 I/O pins (TFS0,
RFS0, DT0, DR0, SCLK0)
SPORT15I/OSerial port 1 I/O pins
or
IRQ1 (TFS1)1IExternal interrupt request #1
IRQ0 (RFS1)1IExternal interrupt request #0
SCLK11OProgrammable clock output
FO (DT1)1OFlag Output pin
FI (DR1)1IFlag Input pin
FL2–03OGeneral purpose flag output
pins
VDD6Power supply pins
GND11Ground pins
PWD1IPowerdown pin
PWDACK1OPowerdown acknowledge pin
Host Interface PortThe ADSP-217x host interface port is a parallel I/O port that al-
lows for an easy connection to a host processor. Through the
HIP, the ADSP-217x can be used as a memory-mapped periph-
eral to a host computer. The HIP can be thought of as an area
of dual-ported memory, or mailbox registers, that allow commu-
nication between the computational core of the ADSP-217x and
the host computer.
The HIP is completely asynchronous. The host processor can
write data into the HIP while the ADSP-217x is operating at full
speed.
The HIP can be configured with the following pins:
• HSIZE configures HIP for 8-bit or 16-bit communication with
the host processor.
• BMODE (when MMAP = 0) determines whether the ADSP-
217x boots from the host processor (through the HIP) or ex-
ternal EPROM (through the data bus).
• HMD0 configures the bus strobes as separate read and write
strobes, or a single read/write select and a host data strobe.
• HMD1 selects separate address (3-bit) and data (16-bit)
buses, or a multiplexed, 16-bit address/data bus with address
latch enable.
Tying these pins to appropriate values configures the ADSP-
217x for straight-wire interface to a variety of industry-standard
microprocessors and microcomputers.
In 8-bit reads, the ADSP-217x three-states the upper eight bits
of the bus. When the host processor writes an 8-bit value to the
HIP, the upper eight bits are all zeros. For additional informa-
tion refer to the ADSP-2100 Family User’s Manual.
HIP OperationThe HIP contains six data registers (HDR5–0) and two status
registers (HSR7–6) with an associated HMASK register for
masking interrupts from individual HIP data registers. All HIP
data registers are memory-mapped into the internal data
memory of the ADSP-217x. HIP transfers can be managed us-
ing either interrupts or a polling scheme. These registers are
shown in the section “ADSP-217x Registers.”
The HIP allows a software reset to be performed by the host
processor. The internal software reset signal is asserted for five
ADSP-217x processor cycles.
InterruptsThe interrupt controller allows the processor to respond to the
eleven possible interrupts and reset with minimum overhead.
The ADSP-217x provides up to three external interrupt input
pins, IRQ0, IRQ1 and IRQ2. IRQ2 is always available as a dedi-
cated pin; SPORT1 may be reconfigured for IRQ0, IRQ1, and
the flags. The ADSP-217x also supports internal interrupts from
the timer, the host interface port, the two serial ports, software,
and the powerdown control circuit. The interrupt levels are in-
ternally prioritized and individually maskable (except power-
down and reset). The input pins can be programmed to be
either level- or edge-sensitive. The priorities and vector ad-
dresses of all interrupts are shown in Table II, and the interrupt
registers are shown in Figure 2.
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected.The powerdown interrupt is nonmaskable.
The ADSP-217x masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect autobuffering.
The interrupt control register, ICNTL, allows the external in-
terrupts to be either edge- or level-sensitive. Interrupt routines
can either be nested with higher priority interrupts taking prece-
dence or processed sequentially.
The IFC register is a write-only register used to force and clear
interrupts generated from software.
Table II.Interrupt Priority & Interrupt Vector AddressesOn-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling.
The stacks are twelve levels deep to allow interrupt nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
When you reset the processor, the interrupt servicing is enabled.
Figure 2.Interrupt Registers
ADSP-2171/ADSP-2172/ADSP-2173
LOW POWER OPERATIONThe ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Powerdown
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
PowerdownThe ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of powerdown fea-
tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
• Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100 μA in some modes.
• Quick recovery from powerdown. The processor begins ex-
ecuting instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 100 CLKIN cycle startup.
• Powerdown is initiated by either the powerdown pin (PWD)
or the software powerdown force bit.
• Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
powerdown state.
• The RESET pin also can be used to terminate powerdown,
and the host software reset feature can be used to terminate
powerdown under certain conditions.
• Powerdown acknowledge pin indicates when the processor has
entered powerdown.
IdleWhen the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
Slow IdleThe IDLE instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during IDLE, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACEFigure 3 shows a basic system configuration with the ADSP-
217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be sup-
ported. Programmable wait state generation allows the processor
to interface easily to slow memories. The ADSP-217x also pro-
vides one external interrupt and two serial ports or three exter-
nal interrupts and one serial port.
Clock SignalsThe ADSP-217x can be clocked by either a crystal or by a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the Power-
down State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this powerdown feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, in-
structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Figure 3.ADSP-217x Basic System Configuration
Because the ADSP-217x includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 4. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
Figure 4. External Crystal Connections
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control Reg-
ister, DM[0x3FF3].
ResetThe RESET signal initiates a master reset of the ADSP-217x.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulse width specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an ex-
ternal Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT reg-
ister. When RESET is released, if there is no pending bus re-
quest and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. Then the first instruction is
fetched from internal program memory location 0x0000.
ADSP-2171/ADSP-2172/ADSP-2173
Program Memory InterfaceThe on-chip program memory address bus (PMA) and the on-
chip program memory data bus (PMD) are multiplexed with
on-chip DMA and DMD buses, creating a single external data
bus and a single external address bus. The 14-bit address bus
directly addresses up to 16K words. 10K words of memory for
ADSP-217x with optional 8K ROM and 2K words of memory
for the non-ROM version are on-chip. The data bus is bidirec-
tional and 24 bits wide to external program memory. Program
memory may contain code and data.
The program memory data lines are bidirectional. The program
memory select (PMS) signal indicates access to the program
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and is used as a write strobe.
The read (RD) signal indicates a read operation and is used as a
read strobe or output enable signal.
The ADSP-217x writes data from its 16-bit registers to the 24-
bit program memory using the PX register to provide the lower
eight bits. When it reads data (not instructions) from 24-bit pro-
gram memory to a 16-bit data register, the lower eight bits are
placed in the PX register.
Program Memory Maps
ADSP-217xProgram memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 5 shows the different configura-
tions. When MMAP = 0, internal RAM occupies 2K words be-
ginning at address 0x0000. In this configuration, the boot
loading sequence (described in “Boot Memory Interface”) is au-
tomatically initiated when RESET is released.
Figure 5.ADSP-217x Memory Maps
When MMAP = 1, words of external program memory begin at
address 0x0000 and internal RAM is located in the upper 2K
words, beginning at address 0x3800. In this configuration, pro-
gram memory is not loaded although it can be written to and
read from under program control.
The optional ROM always resides at locations PM[0x0800]
through PM[0x27FF] regardless of the state of the MMAP pin.
The ROM is enabled by setting the ROMENABLE bit in the
Data Memory Wait State control register, DM[0x3FFE]. When
the ROMENABLE bit is set to 1, addressing program memory
in this range will access the on-chip ROM. When set to zero,
addressing program memory in this range will access external
program memory. The ROMENABLE bit is set to 0 on chip re-
set unless MMAP and BMODE = 1.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
Boot Memory InterfaceThe ADSP-217x can load on-chip memory from external boot
memory space. The boot memory space consists of 64K by 8-bit
space, divided into eight separate 8K by 8-bit pages. Three bits
in the system control register select which page is loaded by the
boot memory interface. Another bit in the system control regis-
ter allows the user to force a boot loading sequence under soft-
ware control. Boot loading from page 0 after RESET is initiated
automatically if MMAP = 0.
The boot memory interface can generate 0 to 7 wait states; it
defaults to 7 wait states after RESET. This allows the ADSP-
217x to boot from a single low cost EPROM such as a 27C256.
Program memory is booted one byte at a time and converted to
24-bit program memory words.
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8–D15. To accommodate addressing up to eight
pages of boot memory, the two MSBs of the data bus are used
in the boot memory interface as the two MSBs of the boot space
address.
The ADSP-2100 Family Assembler and Linker support the cre-
ation of programs and data structures requiring multiple boot
pages during execution.
RD and WR must always be qualified by PMS, DMS, or BMS
to ensure the correct program, data, or boot memory accessing.
HIP BootingThe ADSP-217x can also boot programs through its Host Inter-
face Port. If BMODE = 1 and MMAP = 0, the ADSP-217x
boots from the HIP. If BMODE = 0, the ADSP-217x boots
through the data bus (in the same way as the ADSP-2101), as
described above in “Boot Memory Interface.” For additional in-
formation about HIP booting, refer to the ADSP-2100 Family
User’s Manual, Chapter 7, “Host Interface Port.”
The ADSP-2100 Family Development Software includes a util-
ity program called the HIP Splitter. This utility allows the cre-
ation of programs that can be booted via the ADSP-217x’s HIP,
in a similar fashion as EPROM-bootable programs generated by
the PROM Splitter utility.
Stand-Alone ROM ExecutionWhen the MMAP and BMODE pins both are set to 1, the
ROM is automatically enabled and execution commences from
program memory location 0x0800 at the start of ROM. This
feature lets an embedded design operate without external
memory components. To operate in this mode, the ROM coded
program must copy an interrupt vector table to the appropriate
locations in program memory RAM. In this mode, the ROM
enable bit defaults to 1 during reset.
Table III.Boot Summary Table
Ordering Procedure for ADSP-2172 ProcessorsTo place an order for a custom ROM-coded ADSP-2172 pro-
cessor, you must:Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-2172 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-production ROM Products.Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
IBM PC (DOS 2.01 or higher).Place a purchase order with Analog Devices for nonrecurring
engineering charges (NRE) associated with ROM product
development.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks are
identical, and recalculates the checksums for the .EXE file en-
tered into the ROM Manager System. The checksum data, in the
form of a ROM memory map, a hard copy of the .EXE file, and a
ROM Data Verification Form are returned to you for inspection.
A signed ROM Verification Form and a purchase order for pro-
duction units are required prior to any product being manufac-
tured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of the prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for pro-
duction units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
Data Memory InterfaceThe data memory address (DMA) bus is 14 bits wide. The bidi-
rectional external data bus is 24 bits wide, with the upper 16
bits (D8–D23) used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to the
data memory and can be used as a chip select signal. The write
(WR) signal indicates a write operation and can be used as a
write strobe. The read (RD) signal indicates a read operation
and can be used as a read strobe or output enable signal.
The ADSP-217x supports memory-mapped I/O, with the pe-
ripherals memory mapped into the data or program memory ad-
dress spaces and accessed by the processor in the same manner.
Data Memory MapThe on-chip data memory RAM resides in the 2K words of data
memory beginning at address 0x3000, as shown in Figure 6. In
addition, data memory locations from 0x3800 to the end of data
memory at 0x3FFF are reserved. Control registers for the sys-
tem, timer, wait state configuration, host interface port, and se-
rial port operations are located in this region of memory.
The remaining 12K of data memory is external. External data
memory is divided into three zones, each associated with its own
wait state generator. By mapping peripherals into different
zones, you can accommodate peripherals with different wait
state requirements. All zones default to 7 wait states after
RESET. For compatibility with other ADSP-2100 Family pro-
cessors, bit definitions for DWAIT 3 and DWAIT4 are shown
in the Data Memory Wait State Control Register, but they are
not used by the ADSP-217x.
ADSP-2171/ADSP-2172/ADSP-2173
Bus Request & Bus GrantThe ADSP-217x can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
ADSP-217x is not performing an external memory access, then
it responds to the active BR input in the following processor
cycle by:
• three-stating the data and address buses and the PMS, DMS,
BMS, RD, WR output drivers,
• asserting the bus grant (BG) signal, and
• halting program execution.
If the Go Mode is enabled, the ADSP-217x will not halt pro-
gram execution until it encounters an instruction that requires
an external memory access.
If the ADSP-217x is performing an external memory access
when the external device asserts the BR signal, then it will not
three-state the memory interfaces or assert the BG signal until
the processor cycle after the access completes, which can be up
to eight cycles later depending on the number of wait states.
The instruction does not need to be completed when the bus is
granted. If a single instruction requires two external memory ac-
cesses, the bus will be granted between the two accesses.
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program ex-
ecution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
The new Bus Grant Hang logic and associated BGH pin allow
the ADSP-217x to operate in a multiprocessor environment
with a minimal number of “wasted” processor cycles. The bus
grant hang pin is asserted when the ADSP-217x desires a cycle,
but cannot execute it because the bus is granted to some other
processor. With the BGH signal, the other processor(s) in the
system can be alerted that the ADSP-217x is hung and release
the bus by deasserting bus request. Once the bus is released the
ADSP-217x executes the external access and deasserts BGH.
This is a signal to the other processors that external memory is
now available.
ADSP-217X REGISTERSFigure 7 summarizes all the registers in the ADSP-217x. Some
registers store values. For example, AX0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example, ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the numbers of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except for IMASK, ICNTL and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory; that is, registers are accessed by
reading and writing data memory locations rather than register
names. The particular data memory address is shown with each
memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
Figure 7.ADSP-217x Registers Control Register
ADSP-2171/ADSP-2172/ADSP-2173Control Registers
Control Registers
ADSP-2171/ADSP-2172/ADSP-2173
Control Registers
INSTRUCTION SET DESCRIPTIONThe ADSP-217x assembly language instruction set has an alge-
braic syntax that was designed for ease of coding and read-
ability. The assembly language, which takes full advantage of
the processor’s unique architecture, offers the following benefits:
• The algebraic syntax eliminates the need to remember cryptic
assembler mnemonics. For example, a typical arithmetic add
instruction, such as AR = AX0 + AY0, resembles a simple
equation.
• Every instruction assembles into a single, 24-bit word that can
execute in a single instruction cycle.
• The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize internal memory and conform to the ADSP-
217x’s interrupt vector and reset vector map.
• Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can be
checked and the operation executed in the same instruction
cycle.
• Multifunction instructions allow parallel execution of an arith-
metic instruction with up to two fetches or one write to pro-
cessor memory space during a single instruction cycle.
Consult the ADSP-2100 Family User’s Manual for a complete
Biased RoundingA new mode allows biased rounding in addition to the normal
unbiased rounding. When the BIASRND bit is set to 0, the nor-
mal unbiased rounding operations occur. When the BIASRND
bit is set to 1, biased rounding occurs instead of the normal un-
biased rounding. When operating in biased rounding mode all
rounding operations with MR0 set to 0x8000 will round up,
rather than only rounding odd MR1 values up. For example:
MR value before RNDbiased RND resultunbiased RND result
00-0000-7FFF00-0000-7FFF00-0000-7FFF
00-0001-7FFF00-0001-7FFF00-0001-7FFF
This mode only has an effect when the MR0 register contains
0x8000, all other rounding operation work normally. This mode
was added to allow more efficient implementation of bit speci-
fied algorithms which specify biased rounding such as the GSM
speech compression routines. Unbiased rounding is preferred
for most algorithms.
Note:BIASRND bit is Bit 12 of the SPORT0 Autobuffer
Control register.
ADSP-2171/ADSP-2172/ADSP-2173
Example CodeThe following example is a code fragment that performs the
filter tap update for an adaptive (least-mean-squared algorithm)
filter. Notice that the computations in the instructions are
written like algebraic equations.
MF=MX0*MY1 (RND), MX0=DM (I2,M1);/* MF=error*beta */
MR=MX0*MF (RND), AY0=PM (I6,MS);
DO adapt UNTIL CE;
AR=MR1 + AY0, MX0=DM (I2,M1), AY0=PM (I6,M7);
adapt:PM(I6,M6) =AR, MR=MX0*MF (RND);
MODIFY (I2, M3);/* Point to oldest data */
MODIFY (I6, M7);/* Point to start of data */
Interrupt EnableThe ADSP-217x supports an interrupt enable instruction. Inter-
rupts are enabled by default at reset. The instruction source
code is specified as follows:
Syntax:ENA INTS;
Description:Executing the ENA INTS instruction allows all
unmasked interrupts to be serviced again.
Interrupt DisableThe ADSP-217x supports an interrupt disable instruction. The
instruction source code is specified as follows:
Syntax:DIS INTS;
Description:Reset enables interrupt servicing. Executing the
DIS INTS instruction causes all interrupts to be
masked without changing the contents of the
IMASK register. Disabling interrupts does not
affect the autobuffer circuitry, which will operate
normally whether or not interrupts are enabled.
The disable interrupt instruction masks all user
interrupts including the powerdown interrupt.
ADSP-2171/ADSP-2172–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICSNOTESBidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, HD0-HD15/HAD0-HAD15.Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, HSEL, HSIZE, BMODE, HMD0, HMD1, HRD/HWR, HWR/HDS, PWD, HA2/ALE, HA1-0.Output pins: BG, PMS, DMS, BMS, RD, WR, PWDACK, A0-A13, DT0, DT1, CLKOUT, HACK, FL2-0, BGH.Although specified for TTL outputs, all ADSP-2171/ADSP-2172 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, HD0-HD15/HAD0-HAD15.0 V on BR, CLKIN Active (to force three-state condition).Idle refers to ADSP-2171/ADSP-2172 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND. Current reflects
device operation with CLKOUT disabled.Current reflects device operating with no output loads.VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to “Power Dissipation” section.See Chapter 9, of the ADSP-2100 Family User’s Manual for details.Applies to TQFP and PQFP package types.Output pin capacitance is the capacitive load for any three-state output pin.
Specifications subject to change without notice.
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172
MEMORY REQUIREMENTSThis chart links common memory device specification names
and ADSP-2171/ADSP-2172 timing parameters for your
convenience.
ADSP-2171/ADSP-2172
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) TQFP . . . . . . . . . . . . . . . .+280°C
Lead Temperature (5 sec) PQFP . . . . . . . . . . . . . . . . .+280°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ESD SENSITIVITYThe ADSP-217x is an ESD (electrostatic discharge) sensitive device. Electrostatic charges readily
accumulate on the human body and equipment and can discharge without detection. Permanent
damage may occur to devices subjected to high energy electrostatic discharges.
The ADSP-217x features proprietary ESD protection circuitry to dissipate high energy discharges
(Human Body Model). Per method 3015 of MIL-STD-883, the ADSP-217x has been classified as
a Class 1 device.
Proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality. Unused devices must be stored in conductive foam or shunts, and the foam should be
discharged to the destination before devices are removed.
GENERAL NOTESUse the exact timing information given. Do not attempt to de-
rive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add up parameters to derive longer times.
TIMING NOTESSwitching characteristics specify how the processor changes its
signals. You have no control over this timing; it is dependent on
the internal design. Timing requirements apply to signals that
are controlled outside the processor, such as the data input for a
read operation.
Timing requirements guarantee that the processor operates cor-
rectly with another device. Switching characteristics tell you
what the device will do under a given circumstance. Also, use
the switching characteristics to ensure any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
ADSP-2171/ADSP-2172 TIMING PARAMETERS
ADSP-2171/ADSP-2172NOTEApplies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal
oscillator start-up time).
Figure 8.Clock Signals
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172NOTESIf IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on
the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the User’s Manual for further information on interrupt servicing.)Edge-sensitive interrupts require pulse widths greater than 10 ns; level-sensitive interrupts must be held low until serviced.IRQx = IRQ0, IRQ1, and IRQ2.Flag Output = FL0, FL1, FL2, and FO.
Figure 9.Interrupts and Flags
ADSP-2171/ADSP-2172NOTESBR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized
on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.BGH is asserted when the bus is granted and the processor requires control of the bus to continue.
Figure 10.Bus Request–Bus Grant
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172w = wait states x tCK.
Figure 11.Memory Read
ADSP-2171/ADSP-2172w = wait states x tCK.
Figure 12.Memory Write
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172Figure 13.Serial Ports
ADSP-2171/ADSP-2172NOTESStart of Write = HWR Low and HSEL Low.Start of Read = HRD Low and HSEL Low.End of Write = HWR High or HSEL High.End of Read = HRD High or HSEL High.Read Pulse Width = HRD Low and HSEL Low, Write Pulse Width = HWR Low and HSEL Low.
Figure 14.Host Interface Port (HMD1 = 0, HMD0 = 0)
Host Write Cycle
Host Read Cycle
ADSP-2171/ADSP-2172/ADSP-2173
ADSP-2171/ADSP-2172NOTESStart of Write or Read = HDS Low and HSEL Low.End of Write or Read = HDS High and HSEL High.Read or Write Pulse Width = HDS Low and HSEL Low.
Host Write Cycle
Host Read Cycle
