ADSP-2161 ,DSP Microcomputers With ROMFEATURESARITHMETIC UNITSSERIAL PORTS TIMER25 MIPS, 40 ns Maximum Instruction Rate (5 V)ALU MAC SHIF ..
ADSP-2163 ,DSP Microcomputers With ROMOVERVIEW . . . . . . . . . . . . . . . . . . . . 3TIMING NOTES . . . . . . . . . . . . . . . . . . ..
ADSP-2164 ,DSP Microcomputers With ROMFeaturesFeature 2161 2162 2163 2164 2165 2166Data Memory (RAM) 1/2K 1/2K 1/2K 1/2K 4K 4KProgram Mem ..
ADSP-2164 ,DSP Microcomputers With ROMaDSP Microcomputers with ROMADSP-216xSUMMARY FUNCTIONAL BLOCK DIAGRAM16-Bit Fixed-Point DSP Micropr ..
ADSP-2166 ,DSP Microcomputers With ROMOVERVIEWDevelopment ToolsFigure 1 shows a block diagram of the ADSP-216x architecture.The ADSP-216x ..
ADSP-2171BST-133 ,DSP Microcomputeroverview of ADSP-217xof tools for software and hardware system development, supports functionality. ..
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-2161-ADSP-2163-ADSP-2164-ADSP-2166
DSP Microcomputers With ROM
REV.0
DSP Microcomputers with ROM
FUNCTIONAL BLOCK DIAGRAM
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus and Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction
Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
FEATURES
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC and MQFP Packages
GENERAL DESCRIPTIONThe ADSP-216x Family processors are single-chip micro-
computers␣optimized␣for␣digital␣signal␣processing␣(DSP)
and other high speed numeric processing applications. The
ADSP-216x processors are all built upon a common core with
ADSP-2100. Each processor combines the core DSP architec-
ture—computation units, data address generators and program
sequencer—with features such as␣on-chip program ROM and
data memory RAM, a programmable timer and two serial ports.
The ADSP-2165/ADSP-2166 also adds program memory and
power-down mode.
This data sheet describes the following ADSP-216x Family
processors:
ADSP-2161/ADSP-2162/
ADSP-2163/ADSP-2164Custom ROM-programmed DSPs:
ADSP-2165/ADSP-2166ROM-programmed ADSP-216x
processors with power-down and
larger on-chip memories (12K Pro-
gram Memory ROM, 1K Program
Memory RAM, 4K Data Memory
RAM)
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the highest-performance ADSP-216x proces-
sors operate at 25 MHz with a 40 ns instruction cycle time.
Every instruction can execute in a single cycle. Fabrication in
CMOS results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-216x can␣perform␣all of␣the␣following
operations:Generate the next program address•␣Fetch the next instruction•␣Perform one or two data moves•␣Update one or two data address pointers•␣Perform a computation•␣Receive and transmit data via one or two serial ports
Table I shows the features of each ADSP-216x processor.
The ADSP-216x series are memory-variant versions of the
ADSP-2101 and ADSP-2103 that contain factory-programmed
on-chip ROM program memory. These devices offer different
amounts of on-chip memory for program and data storage.
Table I shows the features available in the ADSP-216x series of
custom ROM-coded processors.
The ADSP-216x products eliminate the need for an external
boot EPROM in your system, and can also eliminate the need
for any external program memory by fitting the entire applica-
tion program in on-chip ROM. These devices thus provide an
excellent option for volume applications where board space and
system cost constraints are of critical concern.
ADSP-216x
TABLE OF CONTENTSSUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-Down Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Entering Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Exiting Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . . 10
ADSP-216x Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Procedure for ADSP-216x ROM Processors . . . . 10
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 13
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 14
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 15
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 15
CAPACITIVE LOADING . . . . . . . . . . . . . . . . . . . . . . . . . 15
SPECIFICATIONS–␣(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 16
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SPECIFICATIONS–RECOMMENDED OPERATING
CONDITIONS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 17
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . 17
SPECIFICATIONS–SUPPLY CURRENT AND POWER
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 18
POWER DISSIPATION EXAMPLE . . . . . . . . . . . . . . . . . 19
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
TIMING PARAMETERS
(ADSP-2161/ADSP-2163/ADSP-2165) . . . . . . . . . . . . . . 21
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 21
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 22
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . 23
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 24
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
TIMING PARAMETERS
(ADSP-2162/ADSP-2164/ADSP-2166) . . . . . . . . . . . . . . 28
GENERAL NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
TIMING NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
MEMORY REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . 28
CLOCK SIGNALS AND RESET . . . . . . . . . . . . . . . . . . . 29
INTERRUPTS AND FLAGS . . . . . . . . . . . . . . . . . . . . . . . 30
BUS REQUEST/BUS GRANT . . . . . . . . . . . . . . . . . . . . . 31
MEMORY READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MEMORY WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SERIAL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
PIN CONFIGURATIONS
68-Lead PLCC (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 35
80-Lead MQFP (ADSP-216x) . . . . . . . . . . . . . . . . . . . . . 36
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
80-Lead MQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table I. ADSP-216x ROM-Programmed Processor Features
Development ToolsThe ADSP-216x processors are supported by a complete set of
tools for system development. The ADSP-2100 Family Devel-
opment Software includes C and assembly language tools that
allow programmers to write code for any of the ADSP-216x
processors. The ANSI C compiler generates ADSP-216x assem-
bly source code, while the runtime C library provides ANSI-
standard and custom DSP library routines. The ADSP-216x
assembler produces object code modules that the linker com-
bines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-21xx
systems by providing a full range of emulation functions such
as modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low-cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information are available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional InformationThis data sheet provides a general overview of ADSP-216x
processor functionality. For detailed design information on the
architecture and instruction set, refer to the ADSP-2100 Family
User’s Manual, Third Edition, available from Analog Devices.
ARCHITECTURE OVERVIEWFigure 1 shows a block diagram of the ADSP-216x architecture.
The processors contain three independent computational units:
the ALU, the multiplier/accumulator (MAC), and the shifter.
The computational units process 16-bit data directly and have
provisions to support multiprecision computations. The ALU
performs a standard set of arithmetic and logic operations;
division primitives are also supported. The MAC performs
single-cycle multiply, multiply/add, and multiply/subtract opera-
tions. The shifter performs logical and arithmetic shifts, normal-
ization, denormalization, and derive exponent operations. The
shifter can be used to efficiently implement numeric format control
including multiword floating-point representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-216x executes looped code with zero
overhead—no explicit jump instructions are required to main-
tain the loop.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
ADSP-216xEfficient data transfer is achieved with the use of five internal
buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS and PMS signals indicate which memory space
is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-216x to fetch two operands in a single cycle,
one from program memory and one from data memory. The
processor can fetch an operand from on-chip program memory
and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
One bus grant execution mode (GO Mode) allows the ADSP-
216x to continue running from internal memory. A second
execution mode requires the processor to halt while buses are
granted.
Each ADSP-216x processor can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a masterRESET signal.
external boot memory. Multiple programs can be selected and
loaded from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-216x processors include two synchronous serial
ports (SPORTs) for serial communications and multiprocessor
communication. All of the ADSP-216x processors have two
serial ports (SPORT0, SPORT1).
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal pro-
grammable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
5
R BUS
EXTERNAL
DATA
BUS
EXTERNAL
ADDRESS
BUSFigure 1.ADSP-216x Block Diagram
The ADSP-216x serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-bufferedtransmit and receive function.
Flexible Clocking—Each SPORT can use an external serialclock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framingfor the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulsewidths and
timings.
Different Word Lengths—Each SPORT supports serial dataword lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optionalA-law and m-law companding according to CCITT recommen-
dation G.711.
Flexible Interrupt Scheme—Receive and transmit functionscan generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORTcan automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0 pro-vides a multichannel interface to selectively receive or transmit a
24-word or 32-word, time-division multiplexed serial bit stream;
this feature is especially useful for T1 or CEPT interfaces, or as
a network communication scheme for multiple processors.
Alternate Configuration—SPORT1 can be alternativelyconfigured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
InterruptsThe ADSP-216x’s interrupt controller lets the processor re-
spond to interrupts with a minimum of overhead. Up to three
external interrupt input pins, IRQ0, IRQ1 and IRQ2, are pro-
vided. IRQ2 is always available as a dedicated pin; IRQ1 and
IRQ0 may be alternately configured as part of Serial Port 1. The
ADSP-216x also supports internal interrupts from the timer and
the serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities for each ADSP-216x
processor are shown in Table II.
Table II.␣Interrupt Vector Addresses and PriorityThe ADSP-216x uses a vectored interrupt scheme: when an
interrupt is acknowledged, the processor shifts program control
to the interrupt vector address corresponding to the interrupt
received. Interrupts can be optionally nested so that a higher
priority interrupt can preempt the currently executing interrupt
service routine. Each interrupt vector location is four instruc-
tions in length so that simple service routines can be coded
entirely in this space. Longer service routines require an addi-
tional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on Bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only regis-
ter that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the inter-
rupt instruction is executed.
Pin DefinitionsPin Function Descriptions show pin definitions for the ADSP-
216x processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACEFigure 3 shows a typical system for the ADSP-216x with two
serial I/O devices, an optional external program and data
memory. A total of 12K words of data memory and 15K words
of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-216x processors also provide either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock SignalsThe ADSP-216x processors’ CLKIN input may be driven by a
crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the ADSP-216x processors include an on-chip oscilla-
tor circuit, an external crystal may also be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in Figure 2. A parallel-
ADSP-216xFigure 2.External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
ResetThe RESET signal initiates a complete reset of the ADSP-216x.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulsewidth specification, tRSP.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the chip
is configured for booting, with MMAP = 0). The first instruction is
then fetched from internal program memory location 0x0000.
PIN FUNCTION DESCRIPTIONSRESETIRQ2BRBGPMSDMSBMSRDWR
MMAP
CLKIN, XTAL
CLKOUT
VDD
NOTESUnused data bus lines may be left floating.BR must be tied high (to VDD) if not used.Only on ADSP-2165/ADSP-2166.
Program Memory InterfaceThe on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single exter-
nal data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
The external address bus is 14 bits wide. For the ADSP-216x,
these lines can directly address up to 16K words, of which 2K
are on-chip.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The ADSP-216x processors write data from their 16-bit regis-
ters to 24-bit program memory using the PX register to provide
the lower eight bits. When the processor reads 16-bit data from
24-bit program memory to a 16-bit data register, the lower eight
bits are placed in the PX register.
The program memory interface can generate 0 to 7 wait states for
external memory devices; default is to 7 wait states after RESET.
Program Memory MapsProgram memory can be mapped in two ways, depending on the
state of the MMAP pin. Figure 4 shows the program memory
map for the ADSP-2165/ADSP-2166. Figures 5 and 6 show the
program memory maps for the ADSP-2161/ADSP-2162 and
ADSP-2163/ADSP-2164, respectively.
ADSP-2165/ADSP-2166When MMAP = 0, on-chip program memory ROM occupies
12K words beginning at address 0x0000. Internal program
memory RAM occupies 1K words beginning at address 0x3000.
Off-chip program memory uses the 2K words beginning at
address 0x3800. The ADSP-2165/ADSP-2166 does not support
boot memory.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 10K words of on-chip program memory
ROM at 0x800 to 0x2FFF, and the remainder 2K words of
program memory ROM is at 0x3800 to 0x3FFF. Internal pro-
gram memory RAM occupies 1K words at address 0x300 to
0x33FF.
Figure 4.ADSP-2165/ADSP-2166 Program Memory Maps
ADSP-2161/ADSP-2162When MMAP = 0, on-chip program memory ROM occupies
8K words beginning at address 0x0000. Off-chip program
memory uses the remaining 8K words beginning at address
0x2000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 6K words of on-chip program memory ROM
are at 0x0800 to 0x1FF0, and the remainder 2K words of pro-
gram memory ROM is at 0x3800 to 0x3FFF. An additional 6K
of off-chip program memory is at 0x2000 to 0x37FF.
SCLK
DT OR FO
DR OR FIFigure 3.Basic System Configuration
ADSP-216x
ADSP-2163/ADSP-2164When MMAP = 0, on-chip program memory ROM occupies
4K words beginning at address 0x0000. Off-chip program
memory uses the remaining 12K words beginning at address
0x1000.
When MMAP = 1, 2K words of off-chip program memory begin
at address 0x0000. 2K words of on-chip program memory ROM
is at 0x0800 to 0x0FF0, and the remainder 2K words of pro-
gram memory ROM is at 0x3800 to 0x3FFF. An additional
10K of off-chip program memory is at 0x1000 to 0x37FF.
MMAP = 0
MMAP = 1
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
0x0000
0x0FF0
0x0FFF
0x1000
0x3FFF
0x07FF
0x0800
0x37FF
0x3800Figure 6.ADSP-2163/ADSP-2164 Program Memory Maps
Data Memory InterfaceThe data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-216x processors support memory-mapped I/O, with
the peripherals memory-mapped into the data memory address
space and accessed by the processor in the same manner as data
memory.
Data Memory MapFor the ADSP-2165/ADSP-2166, on-chip data memory RAM
resides in the 4K words beginning at address 0x2000, as shown
in Figure 7. Data memory locations from 0x3000 to the end of
data memory at 0x3FFF are reserved. Control and status regis-
ters for the system, timer, wait-state configuration, and serial port
operations are located in this region of memory.
The remaining 8K of data memory is located off-chip. This
external data memory is divided into three zones, each associ-
ated with its own wait-state generator. This allows slower pe-
ripherals to be memory-mapped into data memory for which
wait states are specified. By mapping peripherals into different
zones, you can accommodate peripherals with different wait-
state requirements. All zones default to 7 wait states afterRESET.
Figure 7.ADSP-2165/ADSP-2166 Data Memory Map
ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164For the ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164, on-
chip data memory RAM resides in the 512 words beginning at
address 0x3800, also shown in Figure 8. Data memory locations
from 0x3A00 to the end of data memory at 0x3FFF are reserved.
Control and status registers for the system, timer, wait-state
configuration, and serial port operations are located in this
region of memory.
Figure 8.ADSP-2161/ADSP-2162/ADSP-2163/ADSP-2164
Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
Bus InterfaceThe ADSP-216x processors can relinquish control of their data
and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the ADSP-216x is not performing an external
memory access, it responds to the active BR input in the next
cycle by:Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,Asserting the bus grant (BG) signal, and halting program
execution.
If the Go mode is set, however, the ADSP-216x will not halt
program execution until it encounters an instruction that
requires an external memory access.
If the ADSP-216x is performing an external memory access
when the external device asserts the BR signal, it will not three-
state the memory interfaces or assert the BG signal until the
cycle after the access completes (up to eight cycles later depend-
ing on the number of wait states). The instruction does not need
to be completed when the bus is granted; the ADSP-21xx will
grant the bus between two memory accesses if an instruction
requires more than one external memory access.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point at which it stopped.
The bus request feature operates at all times, including when the
processor is booting and when RESET is active. If this feature is
not used, the BR input should be tied high (to VDD).
POWER-DOWNThe ADSP-2165/ADSP-2166 processors have a low power
feature that lets the processor enter a very low power dormant
state through hardware or software control. A list of power-
down features follows:Processor registers and on-chip memory contents are main-
tained during power-down.Power-down mode holds the processor in CMOS standby
with a maximum current of less than 100 mA in some modes.Support for an externally generated TTL or CMOS proces-
sor clock. The external clock can continue running during
power-down without affecting the lowest power rating.Support for crystal operation includes disabling the oscillator
to save power. (The processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabilize).When power-down mode is enabled, powering down of the
processor can be initiated either by externally generatedIRQ2 interrupt or by using the IRQ2 force bit in the IFC
register.Power-Down Acknowledge Pin (PWDACK) indicates when
the processor has entered power-down.Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down.Context clear/save control allows the processor to continueLow-to-high transition of the power-down flag input pin
(PWDFLAG) can be used to terminate power-down.The RESET pin also can also be used to terminate
power-down.
Power-Down ControlSeveral parameters of power-down operation can be controlled
through control bits of the “power-down/sportl autobuffer con-
trol register.” This control register is memory-mapped at loca-
tion 0x3FEF and the power-down control bits are as follows:
bit[15] xtal: xtal pin disable during power-down
1 = disabled, 0 = enable (default)
bit[14] pwdflag: (read only )
when pwdena = 1, the value of bit [14] pwdflag is equal to the
status of the pwdflag input pin.
when pwdena = 0, the value of bit [14] pwdflag is equal to 0.
bit[13] pwdena: power-down enable
1 = enable, 0 = disable (default)
if pwdena is set to 0, then the output pin PWDACK is driven
low and the input pin PWDFLAG is disabled
Note: It is not recommended that power-down enable be set or
cleared during an IRQ2 interrupt.
bit[12] pucr: power-up context reset
1 = soft reset, 0 = resume execution (default)
Entering Power-DownThe power-down sequence is defined as follows:Enable power-down logic by setting the pwdena bit in the
power-down/sportl autobuffer control register.
Note: In order to power-down, the PWDENA bit must be set
before the IRQ2 interrupt is initiated.Initiate the power-down sequence by generating an IRQ2
interrupt either externally or by software use of the IFC
register.The processor vectors to the IRQ2 interrupt vector located at
0x0004.Any number of housekeeping instructions, starting at loca-
tion 0x0004 can be executed prior to the processor entering
the power-down mode.The processor enters the power-down mode when the pro-
cessor executes an IDLE instruction while executing theIRQ2 interrupt routine.
Notes:If an RTI instruction is executed before the processor en-
counter an IDLE instruction, then the processor returns
from the IRQ2 interrupt and the power-down sequence is
aborted.The user can differentiate between a “normal” IRQ2 inter-
rupt and a “power-down” IRQ2 interrupt by resetting the
PWDFLAG pin and checking the status of this pin by testing
the PWDFLAG bit in the power-down/SPORT1 autobuffer
control register located at DM[0x3FEF].
ADSP-216x
Exiting Power-DownThe power-down mode can be exited with the use of the
PWDFLAG or RESET pin. Applying a low-to-high transition to
the PWDFLAG pin takes the processor out of power-down
mode. In this case, a delay of 4096 cycles is automatically in-
duced by the processor. Also, depending on the status of the
power-up context reset bit (pucr), the processor eithercontinues to execute instructions following the IDLE instruc-
tion that caused the power-down. A RTI instruction is re-
quired to pass control back to the main routine (pucr = 0)resumes operation from power-down by clearing the PC,
STATUS, LOOP and CNTR stack. The IMASK and
ASTAT registers are set to 0 and the SSTAT goes to 0x55.
The processor then starts executing instructions from the
address zero (pucr = 1).
In the case where the power-down mode is exited by asserting
the RESET pin, the processor state is reset and instruction are
executed from address 0x0000. The RESET pin in this case
must be held low long enough for the external crystal (if any)
and the on-chip PLL to stabilize and lock.
Low Power IDLE InstructionThe IDLE instruction places the ADSP-216x processor in low
power state in which it waits for an interrupt. When an interrupt
occurs, it is serviced and execution continues with instruction
following IDLE. Typically this next instruction will be a JUMP
back to the IDLE instruction. This implements a low power
standby loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
IDLE n;
where n = 16, 32, 64 or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other inter-
nal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an en-
abled interrupt, the processor will stay in the IDLE state for up
to a maximum of n CLKIN cycles, where n is the divisor speci-
fied in the instruction, before resuming normal operation.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is increased
by n, the clock divisor. When an enabled interrupt is received,
the ADSP-216x will remain in the IDLE state for up to a maxi-
mum of n CLKIN cycles (where n = 16, 32, 64 or 128) before
resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
ADSP-216x PrototypingYou can prototype your ADSP-216x system with either ADSP-
2101 or ADSP-2103 RAM-based processors. When code is fully
developed and debugged, it can be submitted to Analog Devices
for conversion into an ADSP-216x ROM product.
The ADSP-2101 EZ-ICE emulator can be used for development
of ADSP-216x systems. For the 3.3 V ADSP-2162/ADSP-2164
and ADSP-2166, a voltage converter interface board provides
3.3 V emulation.
Additional overlay memory is used for emulation of ADSP-
2161/ADSP-2162 systems. It should be noted that due to the
use of off-chip overlay memory to emulate the ADSP-2161/
ADSP-2162, a performance loss may be experienced when both
executing instructions and fetching program memory data from
the off-chip overlay memory in the same cycle. This can be
overcome by locating program memory data in on-chip memory.
Ordering Procedure for ADSP-216x ROM ProcessorsTo place an order for a custom ROM-coded ADSP-2161,
ADSP-2162, ADSP-2163, ADSP-2164 , ADSP-2165 or ADSP-
2166 processor, you must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-216x ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Preproduction ROM Products
2. Return the forms to Analog Devices along with two copies of the
Memory Image File (.EXE file) of your ROM code. The files must
be supplied on two 3.5" or 5.25" floppy disks for the IBM PC
(DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being manu-
factured. Prototype units may be applied toward the minimum
order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
Instruction SetThe ADSP-216x assembly language uses an algebraic syntax for
ease of coding and readability. The sources and destinations of
computations and data movements are written explicitly in each
assembly statement, eliminating cryptic assembler mnemonics.
Every instruction assembles into a single 24-bit word and executes
in a single cycle. The instructions encompass a wide variety of
instruction types along with a high degree of operational
parallelism. There are five basic categories of instructions: data
move instructions, computational instructions, multifunction
instructions, program flow control instructions and miscella-
neous instructions. Multifunction instructions perform one or
two data moves and a computation.
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
ALU Instructions[IF cond]AR|AF=xop + yop [+ C] ;Add/Add with Carryxop – yop [+ C– 1] ;Subtract X – Y/Subtract X – Y with Borrowyop – xop [+ C– 1] ;Subtract Y – X/Subtract Y – X with Borrowxop AND yop ;ANDxop OR yop ;ORxop XOR yop ;XORPASS xop ;Pass, Clear– xop ;NegateNOT xop ;NOTABS xop ;Absolute Valueyop + 1 ;Incrementyop – 1 ;DecrementDIVS yop, xop ;DivideDIVQ xop ;
MAC Instructions[IF cond]MR|MF=xop * yop ;MultiplyMR + xop * yop ;Multiply/AccumulateMR – xop * yop ;Multiply/SubtractMR ;Transfer MR
=0 ;Clear
IF MV SAT MR ;Conditional MR Saturation
Shifter Instructions[IF cond]SR = [SR OR] ASHIFT xop ;Arithmetic Shift
[IF cond]SR = [SR OR] LSHIFT xop ;Logical Shift
SR = [SR OR] ASHIFT xop BY
;Arithmetic Shift Immediate
SR = [SR OR] LSHIFT xop BY ;Logical Shift Immediate
[IF cond]SE = EXP xop ;Derive Exponent
[IF cond]SB = EXPADJ xop ;Block Exponent Adjust
[IF cond]SR = [SR OR] NORM xop ;Normalize
Data Move Instructions
reg = reg ;Register-to-Register Move
reg = ;Load Register Immediate
reg = DM () ;Data Memory Read (Direct Address)
dreg = DM (Ix , My) ;Data Memory Read (Indirect Address)
dreg = PM (Ix , My) ;Program Memory Read (Indirect Address)
DM () = reg ;Data Memory Write (Direct Address)
DM (Ix , My) = dreg ;Data Memory Write (Indirect Address)
PM (Ix , My) = dreg ;Program Memory Write (Indirect Address)
Multifunction Instructions
|| , dreg = dreg ;Computation with Register-to-Register Move
|| , dreg = DM (Ix , My) ;Computation with Memory Read
|| , dreg = PM (Ix , My) ;Computation with Memory Read
DM (Ix , My) = dreg , || ;Computation with Memory Write
PM (Ix , My) = dreg , || ;Computation with Memory Write
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;Data & Program Memory Read
| , dreg = DM (Ix , My) , dreg = PM (Ix , My) ;ALU/MAC with Data & Program Memory Read
ADSP-216x
Program Flow Instructions
DO [UNTIL term] ;Do Until Loop
[IF cond] JUMP (Ix) ;Jump
[IF cond] JUMP ;
[IF cond] CALL (Ix) ;Call Subroutine
[IF cond] CALL ;
IF [NOT ] FLAG_INJUMP ;Jump/Call on Flag In Pin
IF [NOT ] FLAG_INCALL ;
[IF cond] SET|RESET|TOGGLEFLAG_OUT [, ...] ;Modify Flag Out Pin
[IF cond] RTS ;Return from Subroutine
[IF cond] RTI ;Return from Interrupt Service Routine
IDLE [(n)] ;Idle
Miscellaneous Instructions
NOP ;No Operation
MODIFY (Ix , My);Modify Address Register
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;Stack Control
ENA|DISSEC_REG [, ...] ;Mode Control
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
Notation ConventionsIndex registers for indirect addressingModify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
condCondition code for conditional instruction
termTermination code for DO UNTIL loop
dregData register (of ALU, MAC, or Shifter)
regAny register (including dregs)A semicolon terminates the instructionCommas separate multiple operations of a single instruction
[ ]Optional part of instruction
[, ...]Optional, multiple operations of an instruction
option1 | option2List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0*MY1(RND), MX0=DM(I2,M1);{MF=error*beta}
MR=MX0*MF(RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:PM(I6,M6)=AR, MR=MX0*MF(RND);
MODIFY(I2,M3);{Point to oldest data}
MODIFY(I6,M7);{Point to start of data}
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165–RECOMMENDED OPERATING CONDITIONS
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
NOTESBidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.Input-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.Although specified for TTL outputs, all ADSP-21xx outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.6Guaranteed but not tested.Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.0 V on BR, CLKIN Active (to force three-state condition).Applies to PLCC, MQFP package types.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . .–40°C to +85°C
(No Extended Temperature Range)
Storage Temperature Range . . . . . . . . . . . .–65ºC to +150ºC
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . .+300ºC
Lead Temperature (5 sec) PLCC, MQFP, TQFP . . . .+280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
ADSP-216x
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165–SUPPLY CURRENT AND POWER
NOTESCurrent reflects device operating with no output loads.VIN = 0.4 V and 2.4 V.Idle refers to ADSP-21xx state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
For typical supply current (internal power dissipation) figures, see Figure 9.
Specifications subject to change without notice.
FREQUENCY – MHz
IDD DYNAMIC1
POWER – mW
FREQUENCY – MHz
IDD IDLE1,2
POWER – mW
VALID FOR ALL TEMPERATURE GRADES.
1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3MAXIMUM POWER DISSIPATION AT VDD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
FREQUENCY – MHz
IDD IDLE n MODES3
POWER – mW
10.0013.8320.0025.0030.00
Figure 9.ADSP-2161/ADSP-2163/ADSP-2165 (Typical) vs. Frequency
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C · VDD2 ·␣f
C = load capacitance,␣f␣= output switching frequency.
Example:
In an ADSP-2161 application where external data memory is
used and no other outputs are active, power dissipation is calcu-
lated as follows:
Assumptions:External data memory is accessed every cycle with 50% of
the address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.The application operates at VDD = 5.0 V and tCK = 50 ns.
Total Power Dissipation = PINT + (C · VDD2 ·␣f)
PINT = internal power dissipation (from Figure 9).
(C · VDD2 · f) is calculated for each output:
70.0 mW
Total power dissipation for this example = PINT + 70.0 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
␣␣TAMB = TCASE – (PD · qCA)
␣␣TCASE = Case Temperature in °C␣PD = Power Dissipation in WqCA = Thermal Resistance (Case-to-Ambient)qJA = Thermal Resistance (Junction-to-Ambient)qJC = Thermal Resistance (Junction-to-Case)
CAPACITIVE LOADING
Figures 10 and 11 show capacitive loading characteristics for the
ADSP-2161/ADSP-2163/ADSP-2165.
Figure 10.Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
Figure 11.Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
ADSP-2161/ADSP-2163/ADSP-2165
ADSP-216x
TEST CONDITIONS
Figure 12 shows voltage reference levels for ac measurements.
OUTPUT
INPUT
1.5V
2.0V
0.8V
Figure 12.␣Voltage␣Reference␣Levels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured out-
put high or low voltage to a high impedance state. The output
disable time (tDIS) is the difference of tMEASURED and tDECAY, as
shown in Figure 13. The time tMEASURED is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the mea-
sured output high or low voltage.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be ap-
proximated by the following equation:
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
SPECIFICATIONS
ADSP-2161/ADSP-2163/ADSP-2165
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 13. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Figure 13.Output Enable/Disable
Figure 14.Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
ADSP-2162/ADSP-2164/ADSP-2166–RECOMMENDED OPERATING CONDITIONS
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
VIH
VIL
VOH
VOL
IIH
IIL
IOZL
NOTESInput-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.All ADSP-2162, ADSP-2164 and ADSP-2166 outputs are CMOS and will drive to VDD and GND with no dc loads.Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RFS1, TFS1, DT0, SCLK0, RFS0, TFS0.0 V on BR, CLKIN Active (to force three-state condition).Guaranteed but not tested.Applies to PLCC and MQFP package types.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . .–40ºC to +85ºC
Storage Temperature Range . . . . . . . . . . . .–65ºC to +150ºC
Lead Temperature (5 sec) PLCC, MQFP . . . . . . . . . .+280ºC
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at
these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ADSP-216x
SPECIFICATIONS
ADSP-2162/ADSP-2164/ADSP-2166–SUPPLY CURRENT AND POWER
IDD
NOTESCurrent reflects device operating with no output loads.VIN = 0.4 V and 2.4 V.Idle refers to ADSP-216x state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
For typical supply current (internal power dissipation) figures, see Figure 15.
Specifications subject to change without notice.
FREQUENCY – MHz
IDD IDLE1POWER – mW
FREQUENCY – MHz
IDD DYNAMIC1,2
POWER – mW
IDD IDLE n MODES3
POWER – mW
FREQUENCY – MHz
VALID FOR ALL TEMPERATURE GRADES.
1POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2IDLE REFERS TO ADSP-216x OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3MAXIMUM POWER DISSIPATION AT VDD = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
Figure 15.ADSP-2162 Power (Typical) vs. Frequency)
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C · VDD2 ·␣f
C = load capacitance,␣f␣= output switching frequency.
Example:
In an ADSP-2162 application where external data memory is
used and no other outputs are active, power dissipation is calcu-
lated as follows:
Assumptions:External data memory is accessed every cycle with 50% of the␣address pins switching.External data memory writes occur every other cycle with␣50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.The application operates at VDD = 3.3 V and tCK = 100 ns.
Total Power Dissipation = PINT + (C · VDD2 ·␣f)
PINT = internal power dissipation (from Figure 15).
(C · VDD2 · f) is calculated for each output:
Data, WRRD
15.25 mW
Total power dissipation for this example = PINT + 15.25 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
␣␣TAMB = TCASE – (PD · qCA)
␣␣TCASE = Case Temperature in °C␣PD = Power Dissipation in WqCA = Thermal Resistance (Case-to-Ambient)qJA = Thermal Resistance (Junction-to-Ambient)qJC = Thermal Resistance (Junction-to-Case)
ADSP-2162/ADSP-2164/ADSP-2166
CAPACITIVE LOADING
Figures 16 and 17 show capacitive loading characteristics for
the ADSP-2162 and ADSP-2164.
Figure 16.Typical Output Rise Time vs. Load Capaci-
tance, CL (at Maximum Ambient Operating Temperature)
Figure 17. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating
Temperature)
ADSP-216x
SPECIFICATIONS
ADSP-2162/ADSP-2164/ADSP-2166
TEST CONDITIONS
Figure 18 shows voltage reference levels for ac measurements.
OUTPUT
INPUT
Figure 18.␣Voltage Reference Levels␣for␣AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The out-
put disable time (tDIS) is the difference of tMEASURED and tDECAY,
as shown in Figure 19. The time tMEASURED is the interval from
when a reference signal reaches a high or low voltage level to
when the output voltages have changed by 0.5 V from the mea-
sured output high or low voltage.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be ap-
proximated by the following equation:
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are disabled,
the measurement value is that of the last pin to stop driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from when
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in Figure 19. If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Figure 19.Output Enable/Disable
Figure 20.Equivalent Device Loading for AC
Measurements (Except Output Enable/Disable)
