ADSP-21262SKSTZ200 ,SHARC ProcessorFeatures .6Input Data Port (IDP) ....32Dual-Ported On-Chip Memory ...6Parallel Data Acquisition Por ..
ADSP-21262SKSTZ200 ,SHARC Processorapplications(SRU)The ADSP-21262 SHARC DSP is code compatible with all On-chip memory—2M bits of on- ..
ADSP-21266SKBCZ-2B , SHARC Embedded Processor
ADSP-21266SKBCZ-2B , SHARC Embedded Processor
ADSP-21266SKSTZ-1B , SHARC Embedded Processor
ADSP-21362BBCZ-1AA , SHARC Processor
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-21262SKBC-200-ADSP-21262SKBCZ200-ADSP-21262SKSTZ200
SHARC Processor
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SHARC® Processor
Rev. A
SUMMARY
High performance 32-bit/40-bit floating-point processor
optimized for high precision signal processing
applications
The ADSP-21262 SHARC DSP is code compatible with all
other SHARC DSPs
Single-Instruction Multiple-Data (SIMD) computational archi-
tecture—two 32-bit IEEE floating-point/32-bit fixed-
point/40-bit extended precision floating-point computa-
tional units, each with a multiplier, ALU, shifter, and
register file
High bandwidth I/O—A parallel port, SPI port, six serial
ports, digital audio interface (DAI), and JTAG
DAI incorporates two precision clock generators (PCGs), an
input data port (IDP) which includes the parallel data
acquisition port (PDAP), and three programmable timers,
all under software control through the signal routing unit
(SRU)
On-chip memory—2M bits of on-chip SRAM and a dedicated
4M bits of on-chip mask-programmable ROM
Six independent synchronous serial ports provide a variety
of serial communication protocols including TDM and I2S
modes
The ADSP-21262 is available with a 200 MHz core instruction
rate. For complete ordering information, see Ordering
Guide on Page44.Figure 1.Functional Block Diagram
KEY FEATURES
At 200 MHz (5 ns) core instruction rate, the ADSP-21262
operates at 1200 MFLOPS peak/800 MFLOPS sustained
performance whether operating on fixed or floating point
data
400 MMACS sustained performance at 200 MHz
Super Harvard Architecture—three independent buses for
dual data fetch, instruction fetch, and nonintrusive, zero-
overhead I/O
2M bits on-chip dual-ported SRAM (1M bit block 0, 1M bit
block 1) for simultaneous access by core processor and
DMA
4M bits on-chip dual-ported mask-programmable ROM
(2M bits in block 0 and 2M bits in block 1)
Dual data address generators (DAGs) with modulo and bit-
reverse addressing
Zero-overhead looping with single-cycle loop setup, provid-
ing efficient program sequencing
Single instruction multiple data (SIMD) architecture
provides:
Two computational processing elements
Concurrent execution— Each processing element executes
the same instruction, but operates on different data
Parallelism in buses and computational units allows: Sin-
gle cycle executions (with or without SIMD) of a multiply
operation; an ALU operation; a dual memory read or
write; and an instruction fetch
Transfers between memory and core at up to four 32-bit
floating- or fixed-point words per cycle, sustained
2.4G Bytes/s bandwidth at 200 MHz core instruction rate.
In addition, 900M Bytes/sec is available via DMA
Accelerated FFT butterfly computation through a multiply
with add and subtract instruction
DMA controller supports:
22 zero-overhead DMA channels for transfers between
ADSP-21262 internal memory and serial ports (12), the
input data port (IDP) (8), SPI-compatible port (1), and the
parallel port (1)
32-bit background DMA transfers at core clock speed, in par-
allel with full-speed processor execution
Asynchronous parallel/external port provides:
Access to asynchronous external memory
16 multiplexed address/data lines support 24-bit address
external address range with 8-bit data or 16-bit address
external address range with 16-bit data
66M Byte per sec transfer rate for 200 MHz core rate
256 word page boundaries
External memory access in a dedicated DMA channel
8- to 32-bit and 16- to 32-bit word packing options
Programmable wait state options: 2 to 31 CCLK
Digital audio interface (DAI) includes six serial ports, two pre-
cision clock generators, an input data port, three
programmable timers and a signal routing unit
Serial ports provide:
Six dual data line serial ports that operate at up to 50 Mbits/s
for a 200 MHz core on each data line — each has a clock,
frame sync, and two data lines that can be configured as
either a receiver or transmitter pair
Left-justified sample pair and I2S support, programmable
direction for up to 24 simultaneous receive or transmit
channels using two I2S compatible stereo devices per serial
port
TDM support for telecommunications interfaces including
128 TDM channel support for telephony interfaces such as
H.100/H.110
Up to 12 TDM stream support, each with 128 channels per
frame
Companding selection on a per channel basis in TDM mode
Input data port provides an additional input path to the DSP
core configurable as either eight channels of I2S or serial
data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port
Supports receive audio channel data in I2S, left-justified
sample pair, or right-justified mode
Signal routing unit provides configurable and flexible
connections between all DAI components, six serial ports,
an input data port, two precision clock generators, three
timers, 10 interrupts, six flag inputs, six flag outputs, and
20 SRU I/O pins (DAI_Px)
Serial peripheral interface (SPI)
Master or slave serial boot through SPI
Full-duplex operation
Master-slave mode multimaster support
Open drain outputs
Programmable baud rates, clock polarities, and phases
3 Muxed Flag/IRQ lines
1 Muxed Flag/Timer expired line
ROM based security features:
JTAG access to memory permitted with a 64-bit key
Protected memory regions that can be assigned to limit
access under program control to sensitive code
PLL has a wide variety of software and hardware multi-
plier/divider ratios
JTAG background telemetry for enhanced emulation
features
IEEE 1149.1 JTAG standard test access port and on-chip
emulation
Dual voltage: 3.3 V I/O, 1.2 V core
Available in 136-ball BGA and 144-lead LQFP packages
Lead free packages are also available
TABLE OF CONTENTSGeneral Description ..................................................4
ADSP-21262 Family Core Architecture .......................4
SIMD Computational Engine ................................4
Independent, Parallel Computation Units .................5
Data Register File ................................................5
Single-Cycle Fetch of Instruction and Four Operands ..5
Instruction Cache ...............................................5
Data Address Generators With Zero-Overhead
Hardware Circular Buffer Support .......................5
Flexible Instruction Set ........................................6
ADSP-21262 Memory and I/O Interface Features ..........6
Dual-Ported On-Chip Memory ..............................6
DMA Controller .................................................6
Digital Audio Interface (DAI) ................................6
Serial Ports ........................................................6
Serial Peripheral (Compatible) Interface ...................8
Parallel Port ......................................................8
Timers .............................................................8
ROM Based Security ............................................8
Program Booting ................................................8
Phase-Locked Loop ............................................8
Power Supplies ...................................................8
Target Board JTAG Emulator Connector .....................9
Development Tools ................................................9
Designing an Emulator-Compatible DSP
Board(Target) .................................................10
Additional Information .........................................10
Pin Function Descriptions ........................................11
Address Data Pins as FLAGs ..................................14
Boot Modes ........................................................14
Core Instruction Rate to CLKIN Ratio Modes .............14
Address Data Modes .............................................14
ADSP-21262 Specifications .......................................15
Recommended Operating Conditions .......................15
Electrical Characteristics ........................................15
Absolute Maximum Ratings ...................................16
ESD Sensitivity ....................................................16
Timing Specifications ...........................................16
Power-up Sequencing ........................................18
Clock Input .....................................................19
Clock Signals ...................................................19
Interrupts ........................................................20
Core Timer ......................................................20
Timer PWM_OUT Cycle Timing ..........................21
Timer WDTH_CAP Timing ................................21
DAI Pin to Pin Direct Routing .............................22
Precision Clock Generator (Direct Pin Routing) .......23
Flags ..............................................................24
Memory Read–Parallel Port .................................25
Memory Write—Parallel Port ..............................27
Serial Ports ......................................................29
Input Data Port (IDP) ........................................32
Parallel Data Acquisition Port (PDAP) ...................33
SPI Interface—Master ........................................34
SPI Interface—Slave ...........................................35
JTAG Test Access Port and Emulation ...................36
Output Drive Currents ..........................................37
Test Conditions ...................................................37
Capacitive Loading ...............................................37
Environmental Conditions .....................................38
Thermal Characteristics .........................................38
136-Ball BGA Pin Configurations ................................39
144-LQFP Pin Configurations ....................................42
Package Dimensions................................................ 43
Ordering Guide ......................................................44
REVISION HISTORY
4/04–Data Sheet Changed from Rev. 0 to Rev. AAdded notes to AD pins ............................................11
Added VIHCLKIN and VILCLKIN specifications.....................15
Changed specifications (tALERW, and tALEHZ) ................25-28
Updated 136-BGA package drawing ............................43
GENERAL DESCRIPTIONThe ADSP-21262 SHARC DSP is a member of the SIMD
SHARC family of DSPs featuring Analog Devices Super Har-
vard Architecture. The ADSP-21262 is source code compatible
with the ADSP-21160 and ADSP-21161 DSPs as well as with
first generation ADSP-2106x SHARC processors in SISD (Sin-
gle-Instruction, Single-Data) mode. Like other SHARC DSPs,
the ADSP-21262 is a 32-bit/40-bit floating-point processor opti-
mized for high precision signal processing applications with its
dual-ported on-chip SRAM, mask-programmable ROM, multi-
ple internal buses to eliminate I/O bottlenecks, and an
innovative Digital Audio Interface (DAI).
As shown in the functional block diagram onPage1, the ADSP-
21262 uses two computational units to deliver a 5 to 10 times
performance increase over the ADSP-2106x on a range of DSP
algorithms. Fabricated in a state-of-the-art, high speed, CMOS
process, the ADSP-21262 DSP achieves an instruction cycle
time of 5 ns at 200 MHz. With its SIMD computational hard-
ware, the ADSP-21262 can perform 1200 MFLOPS running at
200 MHz.
Table1 shows performance benchmarks for the ADSP-21262.
The ADSP-21262 continues SHARC’s industry leading stan-
dards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include 2 Mbits dual-ported SRAM memory, 4 Mbits
dual-ported ROM, an I/O processor that supports 22 DMA
channels, six serial ports, an SPI interface, external parallel bus,
and Digital Audio Interface (DAI).
The block diagram of the ADSP-21262 onPage1 illustrates the
following architectural features:Two processing elements, each containing an ALU, Multi-
plier, Shifter, and Data Register FileData Address Generators (DAG1, DAG2)Program sequencer with instruction cachePM and DM buses capable of supporting four 32-bit data
transfers between memory and the core at every core pro-
cessor cycleThree Programmable Interval Timers with PWM Genera-
tion, PWM Capture/Pulse Width Measurement, and
External Event Counter CapabilitiesOn-chip dual-ported SRAM (2M bits)On-chip dual-ported mask-programmable ROM (4M bits)JTAG test access port
The block diagram of the ADSP-21262 IOP onPage1, illus-
trates the following architectural features:8- or 16-bit parallel port that supports interfaces to off-chip
memory peripheralsDMA controllerSix full duplex serial portsSPI compatible interfaceDigital Audio Interface that includes two precision clock
generators (PCG), an input data port (IDP), six serial ports,
eight serial interfaces, a 20-bit synchronous parallel input
port, 10 interrupts, six flag outputs, six flag inputs, three
timers, and a flexible signal routing unit (SRU)
Figure2 on Page5 shows one sample configuration of a SPORT
using the precision clock generator to interface with an I2S ADC
and an I2S DAC with a much lower jitter clock than the serial
port would generate itself. Many other SRU configurations are
possible.
ADSP-21262 FAMILY CORE ARCHITECTUREThe ADSP-21262 is code compatible at the assembly level with
the ADSP-21266, ADSP-21160 and ADSP-21161, and with the
first generation ADSP-2106x SHARC DSPs. The ADSP-21262
shares architectural features with the ADSP-2126x and
ADSP-2116x SIMD SHARC family of DSPs, as detailed in the
following sections.
SIMD Computational EngineThe ADSP-21262 contains two computational processing ele-
ments that operate as a Single-Instruction Multiple-Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY and each contains an ALU, multiplier, shifter, and reg-
ister file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the band-
width between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
Table 1.ADSP-21262 Benchmarks (at 200 MHz)Assumes two files in multichannel SIMD mode
Independent, Parallel Computation UnitsWithin each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register FileA general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four OperandsThe ADSP-21262 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure1 on Page1). With the ADSP-21262’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction CacheThe ADSP-21262 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer SupportThe ADSP-21262’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
Figure 2.ADSP-21262 System Sample Configuration
Fourier transforms. The two DAGs of the ADSP-21262 contain
sufficient registers to allow the creation of up to 32 circular buff-
ers (16 primary register sets, 16 secondary). The DAGs
automatically handle address pointer wraparound, reduce over-
head, increase performance, and simplify implementation.
Circular buffers can start and end at any memory location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of parallel
operations for concise programming. For example, the
ADSP-21262 can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
ADSP-21262 MEMORY AND I/O INTERFACE
FEATURESThe ADSP-21262 adds the following architectural features to
the SIMD SHARC family core.
Dual-Ported On-Chip MemoryThe ADSP-21262 contains two megabits of internal SRAM and
four megabits of internal mask-programmable ROM. Each
block can be configured for different combinations of code and
data storage (see ADSP-21262 Memory Map on Page7). Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory, in combination with three separate on-chip
buses, allows two data transfers from the core and one from the
I/O processor, in a single cycle.
The ADSP-21262’s SRAM can be configured as a maximum of
64K words of 32-bit data, 128K words of 16-bit data, 42K words
of 48-bit instructions (or 40-bit data), or combinations of differ-
ent word sizes up to two megabits. All of the memory can be
accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float-
ing-point storage format is supported that effectively doubles
the amount of data that may be stored on-chip. Conversion
between the 32-bit floating-point and 16-bit floating-point for-
mats is performed in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data using the DM bus for
transfers, and the other block stores instructions and data using
the PM bus for transfers.
Using the DM bus and PM buses, with one dedicated to each
memory block assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache.
DMA ControllerThe ADSP-21262’s on-chip DMA controller allows zero-over-
head data transfers without processor intervention. The DMA
controller operates independently and invisibly to the processor
core, allowing DMA operations to occur while the core is simul-
taneously executing its program instructions. DMA transfers
can occur between the ADSP-21262’s internal memory and its
serial ports, the SPI-compatible (Serial Peripheral Interface)
(PDAP), or the parallel port. Twenty-two channels of DMA are
available on the ADSP-21262—one for the SPI interface, 12 via
the serial ports, eight via the Input Data Port, and one via the
processor’s parallel port. Programs can be downloaded to the
ADSP-21262 using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Digital Audio Interface (DAI)The Digital Audio Interface (DAI) provides the ability to con-
nect various peripherals to any of the DSPs 20 DAI pins
(DAI_P[20:1]).
Programs make these connections using the Signal Routing
Unit (SRU, shown in Figure1).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This provides easy use of the
DAI associated peripherals for a much wider variety of applica-
tions by using a larger set of algorithms than is possible with
nonconfigurable signal paths.
The DAI also includes six serial ports, two precision clock gen-
erators (PCGs), an input data port (IDP), six flag outputs and
six flag inputs, and three timers. The IDP provides an additional
input path to the DSP core configurable as either eight channels
of I2S or serial data, or as seven channels plus a single 20-bit
wide synchronous parallel data acquisition port. Each data
channel has its own DMA channel that is independent from the
ADSP-21262's serial ports.
For complete information on using the DAI, see the
ADSP-2126x SHARC DSP Peripherals Manual.
Serial PortsThe ADSP-21262 features six synchronous serial ports that pro-
vide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices such as Analog Devices
AD183x family of audio codecs, DACs, or ADCs. The serial
ports are made up of two data lines, a clock, and frame sync. The
data lines can be programmed to either transmit or receive and
each data line has its own dedicated DMA channel.
Serial ports are enabled via 12 programmable and simultaneous
receive or transmit pins that support up to 24 transmit or 24
receive channels of serial data when all six SPORTs are enabled,
or six full duplex TDM streams of 128 channels per frame.
The serial ports operate at up to one-quarter of the DSP core
clock rate, providing each with a maximum data rate of
50M bits/s for a 200 MHz core. Serial port data can be automat-
ically transferred to and from on-chip memory via dedicated
DMA channels. Each of the serial ports can work in conjunction
with another serial port to provide TDM support. One SPORT
provides two transmit signals while the other SPORT provides
the two receive signals. The frame sync and clock are shared.
Figure 3.ADSP-21262 Memory Map
Serial ports operate in four modes: Standard DSP serial modeMultichannel (TDM) mode2S modeLeft-justified sample pair mode
Left-justified sample pair mode is a mode where in each frame
sync cycle two samples of data are transmitted/received—one
sample on the high segment of the frame sync, the other on the
low segment of the frame sync. Programs have control over var-
ious attributes of this mode.
Each of the serial ports supports the left-justified sample pair
and I2S protocols (I2S is an industry standard interface com-
monly used by audio codecs, ADCs and DACs), with two data
pins, allowing four left-justified Sample Pair or I2S channels
(using two stereo devices) per serial port, with a maximum of up
to 24 audio channels. The serial ports permit little-endian or
big-endian transmission formats and word lengths selectable
from 3 bits to 32 bits. For the left-justified sample pair and I2S
modes, data-word lengths are selectable between 8 bits and 32
bits. Serial ports offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding selection
on a per channel basis. Serial port clocks and frame syncs can be
internally or externally generated.
Serial Peripheral (Compatible) InterfaceSerial Peripheral Interface (SPI) is an industry standard syn-
chronous serial link, enabling the ADSP-21262 SPI-compatible
port to communicate with other SPI-compatible devices. SPI is
an interface consisting of two data pins, one device select pin,
and one clock pin. It is a full-duplex synchronous serial inter-
face, supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21262 SPI compatible peripheral imple-
mentation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21262 SPI
compatible port uses open drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel PortThe Parallel Port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15-0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, for a clock rate of 200 MHz, this is equiv-
alent to 66M Bytes/sec.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(Address Latch Enable) pins are the control pins for the
parallel port.
TimersThe ADSP-21262 has a total of four timers: a core timer able to
generate periodic software interrupts and three general-purpose
timers that can generate periodic interrupts and be indepen-
dently set to operate in one of three modes:Pulse Waveform Generation modePulse Width Count/Capture modeExternal Event Watchdog mode
The core timer can be configured to use FLAG3 as a Timer
Expired output signal, and each general-purpose timer has one
bidirectional pin and four registers that implement its mode of
operation: a 6-bit configuration register, a 32-bit count register,
a 32-bit period register, and a 32-bit pulse width register. A sin-
gle control and status register enables or disables all three
general-purpose timers independently.
ROM Based SecurityThe ADSP-21262 has a ROM security feature that provides
hardware support for securing user software code by preventing
unauthorized reading from the internal code when enabled.
When using this feature, the DSP does not boot-load any exter-
nal code, executing exclusively from internal SRAM/ROM.
Additionally, the DSP is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
Program BootingThe internal memory of the ADSP-21262 boots at system
power-up from an 8-bit EPROM via the parallel port, an SPI
master, an SPI slave or an internal boot. Booting is determined
by the Boot Configuration (BOOTCFG1-0) pins. Selection of
the boot source is controlled via the SPI as either a master or
slave device, or it can immediately begin executing from ROM.
Phase-Locked Loop The ADSP-21262 uses an on-chip Phase-Locked Loop (PLL) to
generate the internal clock for the core. On power-up, the
CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1.
After booting, numerous other ratios can be selected via soft-
ware control. The ratios are made up of software configurable
numerator values from 1 to 32 and software configurable divi-
sor values of 1, 2, 4, 8, and 16.
Power SuppliesThe ADSP-21262 has separate power supply connections for the
internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS)
power supplies. The internal and analog supplies must meet the
1.2 V requirement. The external supply must meet the 3.3 V
requirement. All external supply pins must be connected to the
same power supply.
Note that the analog supply (AVDD) powers the ADSP-21262’s
clock generator PLL. To produce a stable clock, programs
the AVDD pin. Place the filter as close as possible to the pin. For
an example circuit, see Figure4. To prevent noise coupling, use
a wide trace for the analog ground (AVSS) signal and install a
decoupling capacitor as close as possible to the pin. Note that
the AVSS and AVDD pins specified in Figure4 are inputs to the
SHARC and not the analog ground plane on the board.
TARGET BOARD JTAG EMULATOR CONNECTORAnalog Devices DSP Tools product line of JTAG emulators uses
the IEEE 1149.1 JTAG test access port of the ADSP-21262
processor to monitor and control the target board processor
during emulation. Analog Devices DSP Tools product line of
JTAG emulators provides emulation at full processor speed,
allowing inspection and modification of memory, registers, and
processor stacks. The processor’s JTAG interface ensures that
the emulator will not affect target system loading or timing.
For complete information on Analog Devices’ SHARC DSP
Tools product line of JTAG emulator operation, see the appro-
priate emulator hardware user’s guide.
DEVELOPMENT TOOLSThe ADSP-21262 is supported with a complete set of
CROSSCORETM software and hardware development tools,
including Analog Devices emulators and VisualDSP++TM devel-
opment environment. The same emulator hardware that
supports other SHARC processors also fully emulates the
ADSP-21262.
The VisualDSP++ project management environment lets pro-
grammers develop and debug an application. This environment
includes an easy to use assembler (which is based on an alge-
braic syntax), an archiver (librarian/library builder), a linker, a
loader, a cycle-accurate instruction-level simulator, a C/C++
compiler, and a C/C++ runtime library that includes DSP and
mathematical functions. A key point for these tools is C/C++
code efficiency. The compiler has been developed for efficient
translation of C/C++ code to DSP assembly. The SHARC has
architectural features that improve the efficiency of compiled
C/C++ code.
The VisualDSP++ debugger has a number of important fea-
tures. Data visualization is enhanced by a plotting package that
offers a significant level of flexibility. This graphical representa-
tion of user data enables the programmer to quickly determine
the performance of an algorithm. As algorithms grow in com-
plexity, this capability can have increasing significance on the
designer’s development schedule, increasing productivity. Sta-
tistical profiling enables the programmer to nonintrusively poll
to VisualDSP++, enables the software developer to passively
gather important code execution metrics without interrupting
the real-time characteristics of the program. Essentially, the
developer can identify bottlenecks in software quickly and effi-
ciently. By using the profiler, the programmer can focus on
those areas in the program that impact performance and take
corrective action.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved source
and object information)Insert breakpointsSet conditional breakpoints on registers, memory,
andstacksTrace instruction executionPerform linear or statistical profiling of program executionFill, dump, and graphically plot the contents of memoryPerform source level debuggingCreate custom debugger windows
The VisualDSP++ IDDE lets programmers define and manage
DSP software development. Its dialog boxes and property pages
let programmers configure and manage all of the SHARC devel-
opment tools, including the color syntax highlighting in the
VisualDSP++ editor. This capability permits programmers to:Control how the development tools process inputs and
generate outputsMaintain a one-to-one correspondence with the tool’s
command line switches
The VisualDSP++ Kernel (VDK) incorporates scheduling and
resource management tailored specifically to address the mem-
ory and timing constraints of DSP programming. These
capabilities enable engineers to develop code more effectively,
eliminating the need to start from the very beginning, when
developing new application code. The VDK features include
Threads, Critical and Unscheduled regions, Semaphores,
Events, and Device flags. The VDK also supports Priority-based,
Preemptive, Cooperative, and Time-Sliced scheduling
approaches. In addition, the VDK was designed to be scalable. If
the application does not use a specific feature, the support code
for that feature is excluded from the target system.
Because the VDK is a library, a developer can decide whether to
use it or not. The VDK is integrated into the VisualDSP++
development environment, but can also be used via standard
command line tools. When the VDK is used, the development
environment assists the developer with many error-prone tasks
and assists in managing system resources, automating the gen-
eration of various VDK based objects, and visualizing the
system state, when debugging an application that uses the VDK.
VisualDSP++ Component Software Engineering (VCSE) is
Analog Devices’ technology for creating, using, and reusing
software components (independent modules of substantial
functionality) to quickly and reliably assemble software applica-
Figure 4.Analog Power (AVDD) Filter Circuit
the application. Publish component archives from within
VisualDSP++. VCSE supports component implementation in
C/C++ or assembly language.
Use the Expert Linker to visually manipulate the placement of
code and data on the embedded system. View memory utiliza-
tion in a color-coded graphical form, easily move code and data
to different areas of the DSP or external memory with the drag
of the mouse, examine run time stack and heap usage. The
Expert Linker is fully compatible with the existing Linker Defi-
nition File (LDF), allowing the developer to move between the
graphical and textual environments.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC processor PC plug-in cards. Third
party software tools include DSP libraries, real-time operating
systems, and block diagram designtools.
DESIGNING AN EMULATOR-COMPATIBLE DSP
BOARD(TARGET)The Analog Devices family of emulators are tools that every
DSP developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG DSP. Nonintrusive in-
circuit emulation is assured by the use of the processor’s JTAG
interface—the emulator does not affect target system loading or
timing. The emulator uses the TAP to access the internal fea-
tures of the DSP, allowing the developer to load code, set
breakpoints, observe variables, observe memory, and examine
registers. The DSP must be halted to send data and commands,
but once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on sys-
tem timing.
To use these emulators, the target board must include a header
that connects the DSP’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website ()—
use site search on “EE-68.” This document is updated regularly
to keep pace withimprovements to emulator support.
ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-21262
architecture and functionality. For detailed information on the
ADSP-2126x family core architecture and instruction set, refer
to the ADSP-2126x DSP Core Manual and the ADSP-21160
SHARC DSP Instruction Set Reference.
PIN FUNCTION DESCRIPTIONSADSP-21262 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs iden-
tified as asynchronous (A) can be asserted asynchronously to
CLKIN (or to TCK for TRST). Tie or pull unused inputs to
VDDEXT or GND, except for the following:DAI_Px, SPICLK, MISO, MOSI, EMU, TMS,TRST, TDI,
and AD15-0 (NOTE: These pins have pull-up resistors.)
The following symbols appear in the Type column of Table2:
A = Asynchronous, G = Ground, I=Input, O = Output, P =
Power Supply, S = Synchronous, (A/D) = Active Drive, (O/D) =
Open Drain, and T = Three-State.
Table 2.Pin Descriptions
Table 2.Pin Descriptions (Continued)
RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.Output only is a three-state driver with its output path always enabled.Input only is a three-state driver with both output paths.Three-state is a three-state driver.
Table 2.Pin Descriptions (Continued)
ADDRESS DATA PINS AS FLAGSTo use these pins as flags (FLAGS15-0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port.
BOOT MODES
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
ADDRESS DATA MODESThe following table shows the functionality of the AD pins for
8-bit and 16-bit transfers to the parallel port. For 8-bit data
transfers, ALE latches address bits A23-A8 when asserted, fol-
lowed by address bits A7-A0 and data bits D7-D0 when
deasserted. For 16-bit data transfers, ALE latches address bits
A15-A0 when asserted, followed by data bits D15-D0 when
deasserted.
Table 3.AD[15:0] to Flag Pin Mapping
Table 4.Boot Mode Selection
Table 5.Core Instruction Rate/ CLKIN Ratio Selection
Table 6.Address/Data Mode Selection
ADSP-21262 SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS Specifications subject to change without notice.Applies to input and bidirectional pins: AD15-0, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, SPIDS, BOOTCFGx, CLKCFGx, RESET, TCK, TMS, TDI, TRST.Applies to input pin CLKIN.See Thermal Characteristics on Page38 for information on thermal specifications.See Engineer-to-Engineer Note (No. 216) for further information.Specifications subject to change without notice.Applies to output and bidirectional pins: AD15-0, RD, WR, ALE, FLAG3-0, DAI_Px, SPICLK, MOSI, MISO, EMU, TDO, CLKOUT, XTAL.See Output Drive Currents on Page37 for typical drive current capabilities.Applies to input pins: SPIDS, BOOTCFGx, CLKCFGx, TCK, RESET, CLKIN.Applies to input pins with 22.5 kΩ internal pull-ups: TRST, TMS, TDI.Applies to three-statable pins: FLAG3-0.Applies to three-statable pins with 22.5 kΩ pull-ups: AD15-0, DAI_Px, SPICLK, MISO, MOSI.Applies to open-drain output pins: EMU, MISO, MOSI.Typical internal current data reflects nominal operating conditions.See Engineer-to-Engineer Note (No. 216) for further information.Characterized, but not tested.Characterized, but not tested.Applies to all signal pins.
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITY
TIMING SPECIFICATIONSThe ADSP-21262’s internal clock (a multiple of CLKIN) pro-
vides the clock signal for timing internal memory, processor
core, serial ports, and parallel port (as required for read/write
strobes in asynchronous access mode). During reset, program
the ratio between the DSP’s internal clock frequency and exter-
nal (CLKIN) clock frequency with the CLKCFG1-0 pins. To
determine switching frequencies for the serial ports, divide
down the internal clock, using the programmable divider con-
trol of each port (DIVx for the serial ports).
The ADSP-21262’s internal clock switches at higher frequencies
than the system input clock (CLKIN). To generate the internal
clock, the DSP uses an internal phase-locked loop (PLL). This
PLL-based clocking minimizes the skew between the system
clock (CLKIN) signal and the DSP’s internal clock (the clock
source for the parallel port logic and I/O pads).
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control (Table7 and
Table8).
Figure 5 shows Core to CLKIN ratios of 3:1, 8:1, and 16:1 with
external oscillator or crystal. Note that more ratios are possible
and can be set through software using the power management
control register (PMCTL). For more information, see the
ADSP-2126x SHARC DSP Core Manual.
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results
for an individual device, the values given in this data sheet
reflect statistical variations and worst cases. Consequently, it is
not meaningful to add parameters to derive longer times.
See Figure30 on Page37 under Test conditions for voltage ref-Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADSP-21262 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
Table 7.ADSP-21262 CLKOUT and CCLK Clock
Generation Operation
Table 8.Clock Periodswhere:
SR = serial port-to-core clock ratio (wide range, determined by
SPORT CLKDIV)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by
SPIBAUD register)
DAI_Px = Serial Port Clock
SPICLK = SPI Clock
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching char-
acteristics describe what the processor will do in a given
circumstance. Use switching characteristics to ensure that any
timing requirement of a device connected to the processor (such
as memory) is satisfied.
Timingrequirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a read
operation. Timing requirements guarantee that the processor
operates correctly with other devices.Figure 5.Core Clock and System Clock Relationship to CLKIN
Power-Up SequencingThe timing requirements for DSP startup are given in Table9.
Table 9.Power-Up Sequencing Timing Requirements (DSP Startup)Valid VDDINT/VDDEXT assumes that the supplies are fully ramped to their 1.2 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.Assumes a stable CLKIN signal, after meeting worst-case startup timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for startup time.
Assume a 25 ms maximum oscillator startup time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.Based on CLKIN cycles.Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.The 4096 cycle count depends on tSRST specification in Table11. If setup time is not met, 1 additional CLKIN cycle may be added to the core reset time, resulting in 4097
cycles maximum.
Figure 6.Power-Up Sequencing
Clock Input
Clock SignalsThe ADSP-21262 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21262 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure8 shows
the component connections used for a crystal operating in fun-
damental mode. Note that the clock rate is achieved using a
12.5 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Table 10.Clock InputApplies only for CLKCFG1-0 = 00 and default values for PLL control bits in PMCTL.
2Applies only for CLKCFG1-0 = 01 and default values for PLL control bits in PMCTL.Any changes to PLL control bits in the PMCTL register must meet core clock timing specification tCCLK.
Figure 7.Clock Input
Figure 8.200 MHz Operation with a 12.5 MHz Fundamental Mode
Crystal
Reset
InterruptsThe following timing specification applies to the FLAG0,
FLAG1, and FLAG2 pins when they are configured as IRQ0,
IRQ1, and IRQ2 interrupts. Also applies to DAI_P[20:1] pins
when configured as interrupts.
Core TimerThe following timing specification applies to FLAG3 when it is
configured as the core timer (CTIMER).
Table 11.ResetApplies after the power-up sequence is complete. At power-up, the processor's internal phase-locked loop requires no more than100µs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
Figure 9.Reset
Table 12.InterruptsFigure 10.Interrupts
Table 13.Core Timer
Timer PWM_OUT Cycle TimingThe following timing specification applies to Timer[2:0] in
PWM_OUT (pulse width modulation) mode. Timer signals are
routed to the DAI_P[20:1] pins through the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P[20:1] pins.
Timer WDTH_CAP TimingThe following timing specification applies to Timer[2:0] in
WDTH_CAP (pulse width count and capture) mode. Timer sig-
nals are routed to the DAI_P[20:1] pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P[20:1] pins.
Table 14.Timer[2:0] PWM_OUT TimingFigure 12.Timer[2:0] PWM_OUT Timing
Table 15.Timer[2:0] Width Capture TimingFigure 13.Timer[2:0] Width Capture Timing
DAI Pin to Pin Direct RoutingFor direct pin connections only (for example DAI_PB01_I to
DAI_PB02_O).
Table 16.DAI Pin to Pin RoutingFigure 14.DAI Pin to Pin Direct Routing
