ADSP-21161NKCA-100 ,DSP MicrocomputerGENERAL DESCRIPTIONDMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7The ADSP-2 ..
ADSP-21262SKBC-200 ,SHARC ProcessorCharacteristics .....38Phase-Locked Loop ........8136-Ball BGA Pin Configurations .....39Power Sup ..
ADSP-21262SKBC-200 ,SHARC ProcessorFEATURES Programmable wait state options: 2 to 31 CCLKAt 200 MHz (5 ns) core instruction rate, the ..
ADSP-21262SKBCZ200 ,SHARC ProcessorGeneral Description .....4 Interrupts ..20ADSP-21262 Family Core Architecture .....4 Core Timer 20S ..
ADSP-21262SKBCZ200 ,SHARC Processorfeatures:Asynchronous parallel/external port provides: JTAG access to memory permitted with a 64-bi ..
ADSP-21262SKSTZ200 ,SHARC ProcessorFeatures .6Input Data Port (IDP) ....32Dual-Ported On-Chip Memory ...6Parallel Data Acquisition Por ..
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-21161NCCA100-ADSP-21161NKCA100-ADSP-21161NKCA-100
DSP Microcomputer
S
DSP MicrocomputerREV. A
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.
SUMMARY
High Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Wireless Communications,
Graphics, Imaging, Motor-Control, and Telephony
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Code Compatible with All Other SHARC Family DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Serial Ports Offer I2S Support Via 8 Programmable and
Simultaneous Receive or Transmit Pins, which
Support up to 16 Transmit or 16 Receive Channels of
Audio
Integrated Peripherals—Integrated I/O Processor, Bit On-Chip Dual-Ported SRAM, SDRAM
Controller, Glueless Multiprocessing Features, and
I/O Ports (Serial, Link, External Bus, SPI, and JTAG)
ADSP-21161N Supports 32-Bit Fixed, 32-Bit Float, and
40-Bit Floating-Point Formats
KEY FEATURES
100 MHz (10 ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
600 MFLOPs Peak and 400 MFLOPs Sustained
Performance
225-Ball 17 mm × 17 mm MBGA Package
FUNCTIONAL BLOCK DIAGRAM
ADSP-21161N
KEY FEATURES (continued)
1 M Bit On-Chip Dual-Ported SRAM (0.5 M Bit Block 0,
0.5 M Bit Block 1) for Independent Access by Core
Processor and DMA
200 Million Fixed-Point MACs Sustained Performance
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping with Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and On-Chip
Emulation
Single Instruction Multiple Data (SIMD) Architecture
Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—At Assembly Level, Uses the
Same Instruction Set as Other SHARC DSPs
Parallelism in Buses and Computational Units Enables:
Single-Cycle Execution (with or without SIMD) of: a
Multiply Operation, an ALU Operation, a Dual
Memory Read or Write, and an Instruction Fetch
Transfers Between Memory and Core at Up to Four
32-Bit Floating- or Fixed-Point Words Per Cycle,
Sustained 1.6 Gbytes/s Bandwidth
Accelerated FFT Butterfly Computation through a
Multiply with Add and Subtract
DMA Controller Supports:
14 Zero-Overhead DMA Channels for Transfers between
ADSP-21161N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports,
Link Ports, or Serial Peripheral Interface (SPI-
Compatible)
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
800 M Bytes/s Transfer Rate over IOP Bus
Host Processor Interface to 8-, 16-, and 32-Bit
Microprocessors; the Host Can Directly Read/Write
ADSP-21161N IOP Registers
32-Bit (or up to 48-Bit) Wide Synchronous External Port
Provides:
Glueless Connection to Asynchronous, SBSRAM and
SDRAM External Memories
Memory Interface Supports Programmable Wait State
Generation and Wait Mode for Off-Chip Memory
Up to 50 MHz Operation for Non-SDRAM Accesses
1:2, 1:3, 1:4, 1:6, 1:8 Clock into Core Clock Frequency
Multiply Ratios
24-Bit Address, 32-Bit Data Bus. 16 Additional Data
Lines via Multiplexed Link Port Data Pins Allow
Complete 48-Bit Wide Data Bus for Single-Cycle
External Instruction Execution
Direct Reads and Writes of IOP Registers from Host or
Other 21161N DSPs
62.7 Mega-Word Address Range for Off-Chip SRAM and
SBSRAM Memories
32-48, 16-48, 8-48 Execution Packing for Executing
Instruction Directly from 32-Bit, 16-Bit, or 8-Bit Wide
External Memories
32-48, 16-48, 8-48, 32-32/64, 16-32/64, 8-32/64, Data
Packing for DMA Transfers Directly from 32-Bit,
16-Bit, or 8-Bit Wide External Memories to and from
Internal 32-, 48-, or 64-Bit Internal Memory
Can be Configured to have 48-Bit Wide External Data
Bus, if Link Ports are not Used. The Link Port Data
Lines are Multiplexed with the Data Lines D0 to D15
and are Enabled through Control Bits in SYSCON
SDRAM Controller for Glueless Interface to Low Cost
External Memory
Zero Wait State, 100 MHz Operation for Most Accesses
Extended External Memory Banks (64 M Words) for
SDRAM Accesses
Page Sizes up to 2048 Words
An SDRAM Controller Supports SDRAM in Any and All
Memory Banks
Support for Interface to Run at Core Clock and Half the
Core Clock Frequency
Support for 16 M Bits, 64 M Bits, 128 M Bits, and
256MBits with SDRAM Data Bus Configurations of �4, �8, �16, and �32
254 Mega-Word Address Range for Off-Chip SDRAM
Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-21161Ns, Global Memory,
and a Host
Two 8-Bit Wide Link Ports for Point-to-Point
Connectivity Between ADSP-21161Ns
400 M Bytes/s Transfer Rate over Parallel Bus
200 M Bytes/s Transfer Rate Over Link Ports
Serial Ports Provide:
Four 50 M Bit/s Synchronous Serial Ports with
Companding Hardware
8 Bidirectional Serial Data Pins, Configurable as Either a
Transmitter or Receiver2S Support, Programmable Direction for 8
Simultaneous Receive and Transmit Channels, or Up
to Either 16 Transmit Channels or 16 Receive
Channels
128 Channel TDM Support for T1 and E1 Interfaces
Companding Selection on a Per Channel Basis in TDM
Mode
Serial Peripheral Interface (SPI)
Slave Serial Boot through SPI from a Master SPI Device
Full-Duplex Operation
Master-Slave Mode Multimaster Support
Open-Drain Outputs
Programmable Baud Rates, Clock Polarities and Phases
12 Programmable I/O Pins
1 Programmable Timer
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 3
ADSP-21161N Family Core Architecture . . . . . . . . . 5
SIMD Computational Engine . . . . . . . . . . . . . . . . 5
Independent, Parallel Computation Units . . . . . . . 5
Data Register File . . . . . . . . . . . . . . . . . . . . . . . . . 5
Single-Cycle Fetch of Instruction and
Four Operands . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Instruction Cache . . . . . . . . . . . . . . . . . . . . . . . . . 5
Data Address Generators With Hardware Circular
Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Flexible Instruction Set . . . . . . . . . . . . . . . . . . . . . 5
ADSP-21161N Memory and I/O Interface Features . 5
Dual-Ported On-Chip Memory . . . . . . . . . . . . . . . 5
Off-Chip Memory and Peripherals Interface . . . . . 6
SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . . . . 6
Target Board JTAG Emulator Connector . . . . . . . 7
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Peripheral (Compatible) Interface . . . . . . . . 9
Host Processor Interface . . . . . . . . . . . . . . . . . . . . 9
General-Purpose I/O Ports . . . . . . . . . . . . . . . . . . . 9
Program Booting . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Phase-Locked Loop and Crystal Double Enable . . 9
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Designing an Emulator-Compatible
DSP Board (Target) . . . . . . . . . . . . . . . . . . . . . 10
Additional Information . . . . . . . . . . . . . . . . . . . . . . 11
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . 12
BOOT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . 18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . 19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . 19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . 20
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-up Sequencing – Silicon
Revision 0.3, 1.0, 1.1 . . . . . . . . . . . . . . . . . . . . 22
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory Read – Bus Master . . . . . . . . . . . . . . . . 27
Memory Write – Bus Master . . . . . . . . . . . . . . . . 28
Synchronous Read/Write – Bus Master . . . . . . . . 29
Synchronous Read/Write – Bus Slave . . . . . . . . . . 30
Host Bus Request . . . . . . . . . . . . . . . . . . . . . . . . 31
Asynchronous Read/Write –
Host to ADSP-21161N . . . . . . . . . . . . . . . . . . 33
Three-State Timing – Bus Master, Bus Slave . . . . 35
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . 37
SPI Interface Specifications . . . . . . . . . . . . . . . . . 47
JTAG Test Access Port and Emulation . . . . . . . . 50
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . 51
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output Enable Time . . . . . . . . . . . . . . . . . . . . . . 51
Output Disable Time . . . . . . . . . . . . . . . . . . . . . 51
Example System Hold Time Calculation . . . . . . . 51
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . 52
Environmental Conditions . . . . . . . . . . . . . . . . . . . 52
Thermal Characteristics . . . . . . . . . . . . . . . . . . . 52
225-BALL METRIC MBGA
PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . 53
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . 55
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . 55
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
GENERAL DESCRIPTIONThe ADSP-21161N SHARC DSP is the first low cost derivative
of the ADSP-21160 featuring Analog Devices Super Harvard
Architecture. Easing portability, the ADSP-21161N is source
code compatible with the ADSP-21160 and with first generation
ADSP-2106x SHARCs in SISD (Single Instruction, Single
Data) mode. Like other SHARC DSPs, the ADSP-21161N is a
32-bit processor that is optimized for high performance DSP
applications. The ADSP-21161N includes a 100 MHz core, a
dual-ported on-chip SRAM, an integrated I/O processor with
multiprocessing support, and multiple internal buses to eliminate
I/O bottlenecks.
As was first offered in the ADSP-21160, the ADSP-21161N
offers a Single-Instruction-Multiple-Data (SIMD) architecture.
Using two computational units (ADSP-2106x SHARCs have
one), the ADSP-21161N can double cycle performance versus
the ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power CMOS
process, the ADSP-21161N has a 10 ns instruction cycle time.
With its SIMD computational hardware running at 100 MHz,
the ADSP-21161N can perform 600 million math operations per
second. Table1 shows performance benchmarks for the
ADSP-21161N.
Table 1.Benchmarks (at 100 MHz)
ADSP-21161NThe ADSP-21161N continues SHARC’s industry-leading
standards of integration for DSPs, combining a high performance
32-bit DSP core with integrated, on-chip system features. These
features include a 1 M bit dual ported SRAM memory, host
processor interface, I/O processor that supports 14 DMA
channels, four serial ports, two link ports, SDRAM controller,
SPI interface, external parallel bus, and glueless multiprocessing.
The block diagram of the ADSP-21161N onPage1 illustrates
the following architectural features:Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register FileData Address Generators (DAG1, DAG2)Program sequencer with instruction cachePM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycleInterval timerOn-Chip SRAM (1 M bit)SDRAM Controller for glueless interface to SDRAMsExternal port that supports:Interfacing to off-chip memory peripheralsGlueless multiprocessing support for six ADSP-
21161N SHARCsHost port read/write of IOP registers DMA controllerFour serial portsTwo link portsSPI compatible interfaceJTAG test access port12 General-Purpose I/O Pins
Figure1 shows a typical single-processor system. A multiprocess-
ing system appears in Figure4 on Page8.
Figure 1. System Diagram
ADSP-21161N Family Core ArchitectureThe ADSP-21161N includes the following architectural features
of the ADSP-2116x family core. The ADSP-21161N is code
compatible at the assembly level with the ADSP-21160, ADSP-
21060, ADSP-21061, ADSP-21062, and ADSP-21065L.
SIMD Computational EngineThe ADSP-21161N contains two computational processing
elements that operate as a Single Instruction Multiple Data
(SIMD) engine. The processing elements are referred to as PEX
and PEY, and each contains an ALU, multiplier, shifter, and
register file. PEX is always active, and PEY may be enabled by
setting the PEYEN mode bit in the MODE1 register. When this
mode is enabled, the same instruction is executed in both pro-
cessing elements, but each processing element operates on
different data. This architecture is efficient at executing math
intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is trans-
ferred between memory and the processing elements. When in
SIMD mode, twice the data bandwidth is required to sustain
computational operation in the processing elements. Because of
this requirement, entering SIMD mode also doubles the
bandwidth between memory and the processing elements. When
using the DAGs to transfer data in SIMD mode, two data values
are transferred with each access of memory or the register file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and mul-
tiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision floating-
point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Data Register FileA general-purpose data register file is contained in each process-
ing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2116x enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are referred
to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four OperandsThe ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the
program memory (PM) bus transfers both instructions and data
the processor can simultaneously fetch four operands (two over
each data bus) and an instruction (from the cache), all in a
single cycle.
Instruction CacheThe ADSP-21161N includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This cache
enables full-speed execution of core, looped operations such as
digital filter multiply-accumulates, and FFT butterfly processing.
Data Address Generators With Hardware Circular
BuffersThe ADSP-21161N’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient programming
of delay lines and other data structures required in digital signal
processing, and are commonly used in digital filters and Fourier
transforms. The two DAGs of the ADSP-21161N contain suffi-
cient registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs automati-
cally handle address pointer wrap-around, reduce overhead,
increase performance, and simplify implementation. Circular
buffers can start and end at any memory location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21161N can conditionally execute a multiply, an add, and a
subtract in both processing elements, while branching, all in a
single instruction.
ADSP-21161N Memory and I/O Interface FeaturesThe ADSP-21161N adds the following architectural features to
the ADSP-2116x family core:
Dual-Ported On-Chip MemoryThe ADSP-21161N contains one megabit of on-chip SRAM,
organized as two blocks of 0.5 M bits. Each block can be config-
ured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent
accesses by the core processor and I/O processor. The dual-
ported memory in combination with three separate on-chip buses
allow two data transfers from the core and one from the I/O
processor, in a single cycle. On the ADSP-21161N, the memory
can be configured as a maximum of 32K words of 32-bit data,
64K words of 16-bit data, 21K words of 48-bit instructions (or
40-bit data), or combinations of different word sizes up to one
megabit. All of the memory can be accessed as 16-bit, 32-bit,
48-bit, or 64-bit words. A 16-bit floating-point storage format is
supported that effectively doubles the amount of data that may
be stored on-chip. Conversion between the 32-bit floating-point
and 16-bit floating-point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data using
