ADSP21160MKB-80 ,SHARC, 80 MHz, 600 MFLOPS, 3.3v I/O, 2.5v core, floating pointapplications. The ADSP-21160M Single-cycle Execution (with or without SIMD) of: A includes an 80 MH ..
ADSP-21161NCCA100 ,DSP MicrocomputerFEATURES (continued) 32-48, 16-48, 8-48 Execution Packing for Executing 1 M Bit On-Chip Dual-Ported ..
ADSP-21161NCCAZ100 , SHARC Processor
ADSP-21161NKCA100 ,DSP MicrocomputerFEATURESSingle-Instruction-Multiple-Data (SIMD) Computational 100 MHz (10 ns) Core Instruction Rate ..
ADSP-21161NKCA-100 ,DSP MicrocomputerGENERAL DESCRIPTIONDMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . 7The ADSP-2 ..
ADSP-21262SKBC-200 ,SHARC ProcessorCharacteristics .....38Phase-Locked Loop ........8136-Ball BGA Pin Configurations .....39Power Sup ..
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-21160MKB-80-ADSP21160MKB-80
SHARC, 80 MHz, 600 MFLOPS, 3.3v I/O, 2.5v core, floating point
SHARC®DSP MicrocomputerREV. 0
SHARC is a registered trademark of Analog Devices, Inc.
SUMMARY
High-Performance 32-Bit DSP—Applications in Audio,
Medical, Military, Graphics, Imaging, and
Communication
Super Harvard Architecture—Four Independent Buses
for Dual Data Fetch, Instruction Fetch, and
Nonintrusive, Zero-Overhead I/O
Backwards-Compatible—Assembly Source Level
Compatible with Code for ADSP-2106x DSPs
Single-Instruction-Multiple-Data (SIMD) Computational
Architecture—Two 32-Bit IEEE Floating-Point
Computation Units, Each with a Multiplier, ALU,
Shifter, and Register File
Integrated Peripherals—Integrated I/O Processor, Bit On-Chip Dual-Ported SRAM, Glueless
Multiprocessing Features, and Ports (Serial, Link,
External Bus, and JTAG)
KEY FEATURESMHz (12.5ns) Core Instruction Rate
Single-Cycle Instruction Execution, Including SIMD
Operations in Both Computational Units
480MFLOPS Peak and 320MFLOPS Sustained
Performance (Based on FIR)
Dual Data Address Generators (DAGs) with Modulo and
Bit-Reverse Addressing
Zero-Overhead Looping and Single-Cycle Loop Setup,
Providing Efficient Program Sequencing
IEEE 1149.1 JTAG Standard Test Access Port and
On-Chip Emulation
400-Ball 27����
27mm Metric PBGA Package
FUNCTIONAL BLOCK DIAGRAM
ADSP-21160M
FEATURES (CONTINUED)
Single Instruction Multiple Data (SIMD)
ArchitectureProvides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARCDSPs
Parallelism in Buses and Computational Units Allows:
Single-cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bit On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160M Internal Memory and External
Memory, External Peripherals, Host Processor, Serial
Ports, or Link Ports
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
560M Bytes/s Transfer Rate Over IOP Bus
Host Processor Interface to 16- and 32-Bit
Microprocessors
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ms plus Host
Six Link Ports for Point-To-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 40M Bit/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Up to 40MHz Operation
GENERAL DESCRIPTIONThe ADSP-21160M SHARC DSP is the first processor in
a new family featuring Analog Devices’ Super Harvard
Architecture. Easing portability, the ADSP-21160M is
application source code compatible with first generation
ADSP-2106x SHARC DSPs in SISD (Single Instruction,
Single Data) mode. To take advantage of the processor’s
SIMD (Single Instruction, Multiple Data) capability, some
code changes are needed. Like other SHARCs, the
ADSP-21160M is a 32-bit processor that is optimized for
high performance DSP applications. The ADSP-21160M
includes an 80 MHz core, a dual-ported on-chip SRAM, an
integrated I/O processor with multiprocessing support, and
multiple internal buses to eliminate I/O bottlenecks.
The ADSP-21160M introduces Single-Instruction,
Multiple-Data (SIMD) processing. Using two computa-
tional units (ADSP-2106x SHARC DSPs have one), the
ADSP-21160M can double performance versus the
ADSP-2106x on a range of DSP algorithms.
Fabricated in a state of the art, high speed, low power
CMOS process, the ADSP-21160M has a 12.5ns instruc-
tion cycle time. With its SIMD computational hardware
running at 80MHz, the ADSP-21160M can perform 480
million math operations per second.
Table1 shows performance benchmarks for the
ADSP-21160M.
These benchmarks provide single-channel extrapolations of
measured dual-channel processing performance. For more
information on benchmarking and optimizing DSP code for
single- and dual-channel processing, see Analog Devices’s
website.
The ADSP-21160M continues SHARC’s industry-leading
standards of integration for DSPs, combining a
high-performance 32-bit DSP core with integrated, on-chip
system features. These features include a 4Mbit dual
ported SRAM memory, host processor interface, I/O
processor that supports 14 DMA channels, two serial ports,
six link ports, external parallel bus, and glueless
Table 1. ADSP-21160M Benchmarks
The functional block diagram onpage1 shows a block
diagram of the ADSP-21160M, illustrating the following
architectural features:Two processing elements, each made up of an ALU, Mul-
tiplier, Shifter, and Data Register FileData Address Generators (DAG1, DAG2)Program sequencer with instruction cachePM and DM buses capable of supporting four 32-bit data
transfers between memory and the core every core
processor cycleInterval timerOn-Chip SRAM (4Mbit)External port that supports:Interfacing to off-chip memory peripheralsGlueless multiprocessing support for six
ADSP-21160M SHARCsHost portDMA controllerSerial ports and link portsJTAG test access port
Figure1 shows a typical single-processor system. A multi-
processing system appears in Figure4.
ADSP-21160M Family Core ArchitectureThe ADSP-21160M includes the following archi-
tectural features of the ADSP-2116x family core. The
ADSP-21160M is code compatible at the assembly level
with the ADSP-21060, ADSP-21061, and ADSP-21062.
SIMD Computational EngineThe ADSP-21160M contains two computational process-
ing elements that operate as a Single Instruction Multiple
Data (SIMD) engine. The processing elements are referred
to as PEX and PEY, and each contains an ALU, multiplier,
shifter, and register file. PEX is always active, and PEY may
be enabled by setting the PEYEN mode bit in the MODE1
register. When this mode is enabled, the same instruction
is executed in both processing elements, but each processing
element operates on different data. This architecture is
efficient at executing math-intensive DSP algorithms.
Entering SIMD mode also has an effect on the way data is
transferred between memory and the processing elements.
When in SIMD mode, twice the data bandwidth is required
to sustain computational operation in the processing
elements. Because of this requirement, entering SIMD
mode also doubles the bandwidth between memory and the
processing elements. When using the DAGs to transfer data
in SIMD mode, two data values are transferred with each
access of memory or the register file.
Independent, Parallel Computation Units Within each processing element is a set of computational
units. The computational units consist of an arith-
metic/logic unit (ALU), multiplier, and shifter. These units
perform single-cycle instructions. The three units within
each processing element are arranged in parallel, maximiz-
ing computational throughput. Single multifunction
instructions execute parallel ALU and multiplier opera-
tions. In SIMD mode, the parallel ALU and multiplier
operations occur in both processing elements. These com-
putation units support IEEE 32-bit single-precision
floating-point, 40-bit extended precision floating-point,
and 32-bit fixed-point data formats.
Data Register FileA general-purpose data register file is contained in each
processing element. The register files transfer data between
the computation units and the data buses, and store inter-
mediate results. These 10-port, 32-register (16 primary, 16
secondary) register files, combined with the ADSP-2116x
enhanced Harvard architecture, allow unconstrained data
flow between computation units and internal memory. The
registers in PEX are referred to as R0–R15 and in PEY S0–S15.
Single-Cycle Fetch of Instruction and Four OperandsThe ADSP-21160M features an enhanced Harvard archi-
tecture in which the data memory (DM) bus transfers data,
and the program memory (PM) bus transfers both instruc-
Figure 1. Single-Processor System
ADSP-21160MWith the ADSP-21160M’s separate program and data
memory buses and on-chip instruction cache, the processor
can simultaneously fetch four operands and an instruction
(from the cache), all in a single cycle.
Instruction CacheThe ADSP-21160M includes an on-chip instruction cache
that enables three-bus operation for fetching an instruction
and four data values. The cache is selective—only the
instructions whose fetches conflict with PM bus data
accesses are cached. This cache allows full-speed execution
of core, providing looped operations such as digital filter
multiply- accumulates and FFT butterfly processing.
Data Address Generators with Hardware
CircularBuffersThe ADSP-21160M’s two data address generators (DAGs)
are used for indirect addressing and provide for implement-
ing circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data struc-
tures required in digital signal processing, and are
commonly used in digital filters and Fourier transforms.
The two DAGs of the ADSP-21160M contain sufficient
registers to allow the creation of up to 32 circular buffers
(16 primary register sets, 16 secondary). The DAGs auto-
matically handle address pointer wraparound, reducing
overhead, increasing performance, and simplifying imple-
mentation. Circular buffers can start and end at any
memory location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of
parallel operations, for concise programming. For example,
the ADSP-21160M can conditionally execute a multiply, an
add, and subtract, in both processing elements, while
branching, all in a single instruction.
ADSP-21160M Memory and I/O Interface FeaturesAugmenting the ADSP-2116x family core, the
ADSP-21160M adds the following architectural features:
Dual-Ported On-Chip MemoryThe ADSP-21160M contains four megabits of on-chip
SRAM, organized as two blocks of 2 Mbits each, which can
be configured for different combinations of code and data
storage. Each memory block is dual-ported for single-cycle,
independent accesses by the core processor and I/O proces-
sor. The dual-ported memory in combination with three
separate on-chip buses allows two data transfers from the
core and one from I/O processor, in a single cycle. On the
ADSP-21160M, the memory can be configured as a
maximum of 128K words of 32-bit data, 256K words of
16-bit data, 85K words of 48-bit instructions (or 40-bit
data), or combinations of different word sizes up to four
megabits. All of the memory can be accessed as 16-bit,
32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the
between the 32-bit floating-point and 16-bit floating-point
formats is done in a single instruction. While each memory
block can store combinations of code and data, accesses are
most efficient when one block stores data, using the DM
bus for transfers, and the other block stores instructions and
data, using the PM bus for transfers. Using the DM bus and
PM bus in this way, with one dedicated to each memory
block, assures single-cycle execution with two data trans-
fers. In this case, the instruction must be available in
thecache.
Off-Chip Memory and Peripherals InterfaceThe ADSP-21160M’s external port provides the proces-
sor’s interface to off-chip memory and peripherals. The word off-chip address space is included in the
ADSP-21160M’s unified address space. The separate
on-chip buses—for PM addresses, PM data, DM addresses,
DM data, I/O addresses, and I/O data—are multiplexed at
the external port to create an external system bus with a
single 32-bit address bus and a single 64-bit data bus. The
lower 32 bits of the external data bus connect to even
addresses and the upper 32 bits of the 64 connect to odd
addresses. Every access to external memory is based on an
address that fetches a 32-bit word, and with the 64-bit bus,
two address locations can be accessed at once. When
fetching an instruction from external memory, two 32-bit
data locations are being accessed (16 bits are unused).
Figure3 shows the alignment of various accesses to
externalmemory.
The external port supports asynchronous, synchronous,
and synchronous burst accesses. ZBT synchronous burst
SRAM can be interfaced gluelessly. Addressing of external
memory devices is facilitated by on-chip decoding of
high-order address lines to generate memory bank select
signals. Separate control lines are also generated for simpli-
fied addressing of page-mode DRAM. The ADSP-21160M
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to
DRAM and peripherals with variable access, hold, and
disable time requirements.
DMA ControllerThe ADSP-21160M’s on-chip DMA controller allows
zero-overhead data transfers without processor interven-
tion. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions. DMA transfers can occur between the
ADSP-21160M’s internal memory and external memory,
external peripherals, or a host processor. DMA transfers can
also occur between the ADSP-21160M’s internal memory
and its serial ports or link ports. External bus packing to
16-, 32-, 48-, or 64-bit words is performed during DMA
transfers. Fourteen channels of DMA are available on the
ADSP-21160M—six via the link ports, four via the serial
host processor, other ADSP-21160Ms, memory or I/O
transfers). Programs can be downloaded to the
ADSP-21160M using DMA transfers. Asynchronous
off-chip peripherals can control two DMA channels using
DMA Request/Grant lines (DMAR1–2, DMAG1–2).
Other DMA features include interrupt generation upon
completion of DMA transfers, two-dimensional DMA, and
DMA chaining for automatic linked DMA transfers.
Multiprocessing The ADSP-21160M offers powerful features tailored to
multiprocessing DSP systems as shown in Figure4. The
external port and link ports provide integrated glueless mul-
tiprocessing support.
The external port supports a unified address space (see
Figure2) that allows direct interprocessor accesses of each
ADSP-21160M’s internal memory. Distributed bus arbitra-
tion logic is included on-chip for simple, glueless connection
of systems containing up to six ADSP-21160Ms and a host
or rotating priority. Bus lock allows indivisible read-mod-
ify-write sequences for semaphores. A vector interrupt is
provided for interprocessor commands. Maximum
throughput for interprocessor data transfer is 320M bytes/s
over the external port. Broadcast writes allow simultaneous
transmission of data to all ADSP-21160Ms and can be used
to implement reflective semaphores.
Six link ports provide for a second method of multiprocess-
ing communications. Each link port can support
communications to another ADSP-21160M. Using the
links, a large multiprocessor system can be constructed in a
2D or 3D fashion. Systems can use the link ports and cluster
multiprocessing concurrently or independently.
Link PortsThe ADSP-21160M features six 8-bit link ports that
provide additional I/O capabilities. With the capability of
running at 80MHz rates, each link port can support 80M
bytes/s. Link port I/O is especially useful for point-to-point
interprocessor communication in multiprocessing systems.
The link ports can operate independently and simulta-
neously. Link port data is packed into 48- or 32-bit words,
and can be directly read by the core processor or
DMA-transferred to on-chip memory. Each link port has its
own double-buffered input and output registers.
Clock/acknowledge handshaking controls link port trans-
fers. Transfers are programmable as either transmit receive. For data throughput information, see link port
timing details in Table18 on page34.
Serial PortsThe ADSP-21160M features two synchronous serial ports
that provide an inexpensive interface to a wide variety of
digital and mixed-signal peripheral devices. The serial ports
can operate up to half the clock rate of the core, providing
Figure 2. ADSP-21160M Memory MapFigure 3. ADSP-21160M External Data Alignment Options
ADSP-21160Mtransmit and receive functions provide greater flexibility for
serial communications. Serial port data can be automati-
cally transferred to and from on-chip memory via a
dedicated DMA. Each of the serial ports offers a TDM
tle-endian or big-endian transmission formats, with word
lengths selectable from 3 bits to 32 bits. They offer selectable
synchronization and transmit modes as well as optional
µ-law or A-law companding. Serial port clocks and frame
syncs can be internally or externally generated.
Host Processor InterfaceThe ADSP-21160M host interface allows easy connection
to standard microprocessor buses, both 16-bit and 32-bit,
with little additional hardware required. The host interface
is accessed through the ADSP-21160M’s external port and
is memory-mapped into the unified address space. Four
channels of DMA are available for the host interface; code
and data transfers are accomplished with low software
overhead. The host processor communicates with the
ADSP-21160M’s external bus with host bus request
(HBR), host but grant (HBG), ready (REDY), acknowledge
(ACK), and chip select (CS) signals. The host can directly
read and write the internal memory of the ADSP-21160M,
and can access the DMA channel setup and mailbox regis-
ters. Vector interrupt support provides efficient execution
of host commands.
Program BootingThe internal memory of the ADSP-21160M can be booted
at system power-up from an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot)
pins. 32-bit and 16-bit host processors can be used
forbooting.
Phased Locked LoopThe ADSP-21160M uses an on-chip PLL to generate the
internal clock for the core. Ratios of 2:1, 3:1, and 4:1
between the core and CLKIN are supported. The
CLK_CFG pins are used to select the ratio. The CLKIN
rate is the rate at which the synchronous external
portoperates.
Power SuppliesThe ADSP-21160M has separate power supply connections
for the internal (VDDINT), external (VDDEXT), and analog
(AVDD/AGND) power supplies. The internal and analog
supplies must meet the 2.5V requirement. The external
supply must meet the 3.3V requirement. All external supply
pins must be connected to the same supply.
Note that the analog supply (AVDD) powers the
ADSP-21160M’s clock generator PLL. To produce a stable
clock, the system must provide an external circuit to filter
the power input to the AVDD pin. Place the filter as close as
possible to the pin. For an example circuit, see Figure5. To
prevent noise coupling, use a wide trace for the analog
ground (AGND) signal and install a decoupling capacitor
as close as possible to the pin.
Figure 4. Shared Memory Multiprocessing System
Development ToolsThe ADSP-21160M is supported with a complete set of
software and hardware development tools, including Analog
Devices’ emulators and VisualDSP++1 development envi-
ronment. The same emulator hardware that supports other
ADSP-2116x DSPs, also fully emulates the
ADSP-21160M.
The VisualDSP++ project management environment lets
programmers develop and debug an application. This envi-
ronment includes an easy-to-use assembler that is based on
an algebraic syntax; an archiver (librarian/library builder),
a linker, a loader, a cycle-accurate instruction-level simula-
tor, a C/C++ compiler, and a C/C++ run-time library that
includes DSP and mathematical functions. Two key points
for these tools are:Compiled ADSP-2116x C/C++ code efficiency—the
compiler has been developed for efficient translation of
C/C++ code to ADSP-2116x assembly. The DSP has
architectural features that improve the efficiency of
compiledC/C++code.ADSP-2106x family code compatibility—The assembler
has legacy features to ease the conversion of existing
ADSP-2106x applications to the ADSP-2116x.
Debugging both C/C++ and assembly programs with the
VisualDSP++ debugger, programmers can:View mixed C/C++ and assembly code (interleaved
source and object information)Insert break pointsSet conditional breakpoints on registers, memory, and
stacksTrace instruction executionPerform linear or statistical profiling of program
executionFill, dump, and graphically plot the contents of memorySource level debuggingCreate custom debugger windows
The VisualDSP++ IDE lets programmers define and
manage DSP software development. Its dialog boxes and
property pages let programmers configure and manage all
of the ADSP-2116x development tools, including the syntax
highlighting in the VisualDSP++ editor. This capability
permits:Control how the development tools process inputs and
generate outputs.Maintain a one-to-one correspondence with the tool’s
command line switches.
Analog Devices’ DSP emulators use the IEEE 1149.1 JTAG
test access port of the ADSP-21160M processor to monitor
and control the target board processor during emulation.
The emulator provides full-speed emulation, allowing
inspection and modification of memory, registers, and
processor stacks. Nonintrusive in-circuit emulation is
assured by the use of the processor’s JTAG interface—the
emulator does not affect target system loading or timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the ADSP-2116x processor
family. Hardware tools include ADSP-2116x PC plug-in
cards. Third Party software tools include DSP libraries,
real-time operating systems, and block diagram
designtools.
Designing an Emulator-Compatible DSP Board
(Target)The White Mountain DSP (Product Line of Analog
Devices, Inc.) family of emulators are tools that every DSP
developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1
JTAG Test Access Port (TAP) on each JTAG DSP. The
emulator uses the TAP to access the internal features of the
DSP, allowing the developer to load code, set breakpoints,
observe variables, observe memory, and examine registers.
The DSP must be halted to send data and commands, but
once an operation has been completed by the emulator, the
DSP system is set running at full speed with no impact on
system timing.o use these emulators, the target’s design must include the
interface between an Analog Devices’ JTAG DSP and the
emulation header on a custom DSP target board.
Target Board HeaderThe emulator interface to an Analog Devices’ JTAG DSP
is a 14-pin header, as shown in Figure6. The customer must
supply this header on the target board in order to commu-
nicate with the emulator. The interface consists of a
standard dual row 0.025" square post header, set on
0.1"�0.1" spacing, with a minimum post length of 0.235".
Pin 3 is the key position used to prevent the pod from being
inserted backwards. This pin must be clipped on the
targetboard.
Figure 5. Analog Power (AVDD) Filter Circuit
ADSP-21160MAlso, the clearance (length, width, and height) around the
header must be considered. Leave a clearance of at least
0.15" and 0.10" around the length and width of the header,
and reserve a height clearance to attach and detach the pod
connector.
As can be seen in Figure6, there are two sets of signals on
the header. There are the standard JTAG signals TMS,
TCK, TDI, TDO, TRST, and EMU used for emulation
purposes (via an emulator). There are also secondary JTAG
signals BTMS, BTCK, BTDI, and BTRST that are option-
ally used for board-level (boundary scan) testing.
When the emulator is not connected to this header, place
jumpers across BTMS, BTCK, BTRST, and BTDI as
shown in Figure7. This holds the JTAG signals in the
correct state to allow the DSP to run free. Remove all the
jumpers when connecting the emulator to the JTAG header.
AG Emulator Pod ConnectorFigure8 details the dimensions of the JTAG pod connector
at the 14-pin target end. Figure9 displays the keep-out area
for a target board header. The keep-out area allows the pod
connector to properly seat onto the target board header.
This board area should contain no components (chips,
resistors, capacitors, etc.). The dimensions are referenced
to the center of the 0.25" square post pin.
Design-for-Emulation Circuit InformationFor details on target board design issues including: single
processor connections, multiprocessor scan chains, signal
buffering, signal termination, and emulator pod logic, see
the EE-68: Analog Devices JTAG Emulation Technical
Reference on the Analog Devices website—use site search on
“EE-68” (). This document is updated
regularly to keep pace with improvements to emulator
support.
Additional InformationThis data sheet provides a general overview of the
ADSP-21160M architecture and functionality. For detailed
information on the ADSP-2116x Family core architecture
and instruction set, refer to the ADSP-2116x SHARC DSP
Hardware Reference.
PIN FUNCTION DESCRIPTIONSADSP-21160M pin definitions are listed below. Inputs
identified as synchronous (S) must meet timing require-
ments with respect to CLKIN (or with respect to TCK for
TMS, TDI). Inputs identified as asynchronous (A) can be
Figure 6. JTAG Target Board Connector for JTAG
Equipped Analog Devices DSP (Jumpers in Place)
Figure 7. JTAG Target Board Connector with No Local
Boundary Scan
Figure 8. JTAG Pod Connector Dimensions
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31–0, DATA63–0, FLAG3–0, and inputs
that have internal pull-up or pull-down resistors (PA, ACK,
BRST, PAGE, CLKOUT, MS3–0, RDx, WRx, DMARx,
DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7–0,
LxCLK, LxACK, TMS, TRST and TDI)—these pins can
be left floating. These pins have a logic-level hold circuit
(only enabled on the ADSP-21160M with ID2–0=00x)
that prevents input from floating internally.
The following symbols appear in the Type column of
Table2: A=Asynchronous, G=Ground, I=Input, =Output, P=Power Supply, S=Synchronous,
(A/D)=Active Drive, (O/D)=Open Drain, and =Three-State (when SBTS is asserted, or when the
ADSP-21160M is a bus slave).
Table 2. Pin Function Descriptions
ADSP-21160M
Table 2. Pin Function Descriptions (Continued)
Table 2. Pin Function Descriptions (Continued)
ADSP-21160M
Table 3. Boot Mode Selection
Table 2. Pin Function Descriptions (Continued)
ADSP-21160M SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS Specifications subject to change without notice.
2Applies to input and bidirectional pins: DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, IRQ2–0, FLAG3–0, HBG, CS, DMAR1, DMAR2, BR6–1,
ID2–0, RPBA, PA, BRST, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1,
TCLK0, TCLK1, RCLK0, RCLK1.Applies to input pins: CLKIN, RESET, TRST.
4See Environmental Conditions on page45 for information on thermal specifications.
ELECTRICAL CHARACTERISTICS Specifications subject to change without notice.Applies to output and bidirectional pins: DATA63–0, ADDR31–0, MS3–0, RDx, WRx, PAGE, CLKOUT, ACK, FLAG3–0, TIMEXP, HBG, REDY,
DMAG1, DMAG2, BR6–1, PA, BRST, CIF, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3–0, LxCLK, LxACK,
BMS, TDO, EMU.See Output Drive Currents on page42 for typical drive current capabilities.
ADSP-21160M
ABSOLUTE MAXIMUM RATINGS
ESD SENSITIVITYApplies to input pins with internal pull-ups: DR0, DR1.
6Applies to input pins with internal pull-ups: DMARx, TMS, TDI, TRST.Applies to three-statable pins: DATA63–0, ADDR31–0, PAGE, CLKOUT, ACK, FLAG3–0, REDY, HBG, BMS, BR6–1, TFSx, RFSx, TDO. Applies to three-statable pins with internal pull-ups: DTx, TCLKx, RCLKx, EMU.Applies to three-statable pins with internal pull-ups: MS3–0, RDx, WRx, DMAGx, PA, CIF.Applies to three-statable pins with internal pull-downs: LxDAT7–0, LxCLK, LxACK.Applies to ACK pulled up internally with 2kΩ during reset or ID2–0= 00x.
12The test program used to measure IDD-INPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual
internal power measurements made using typical applications are less than specified. For more information, see Power Dissipation on page42.IDDINHIGH is a composite average based on a range of high activity code. For more information, see Power Dissipation on page42.IDDINLOW is a composite average based on a range of low activity code. For more information, see Power Dissipation on page42.Idle denotes ADSP-21160M state during execution of IDLE instruction. For more information, see Power Dissipation on page42.Characterized, but not tested.
17Applies to all signal pins.Guaranteed, but not tested.
Internal (Core) Supply Voltage (VDDINT)1. . .–0.3 V to +3.0 V
Analog (PLL) Supply Voltage (AVDD) . . . . .–0.3 V to +3.0 V
External (I/O) Supply Voltage (VDDEXT) . . . .–0.3 V to +4.6 V
Input Voltage. . . . . . . . . . . . . . . . . .–0.5 V to VDDEXT+0.5 V
Output Voltage Swing . . . . . . . . . . .–0.5 V to VDDEXT+0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF
Storage Temperature Range. . . . . . . . . . . –65ºC to +150ºC
Lead Temperature (5 seconds). . . . . . . . . . . . . . . . . 185ºCStresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any
other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAUTION:ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V
readily accumulate on the human body and test equipment and can discharge without
detection. Although the ADSP-21160M features proprietary ESD protection
circuitry, permanent damage may occur on devices subjected to high-energy electro-
static discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality.
Timing SpecificationsThe ADSP-21160M’s internal clock switches at higher fre-
quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160M’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre-
quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:tCCLK = (tCK) / CRtLCLK = (tCCLK) � LRtSCLK = (tCCLK) � SR
Where:LCLK = Link Port ClockSCLK = Serial Port ClocktCK = CLKIN Clock PeriodtCCLK = (Processor) Core Clock PeriodtLCLK = Link Port Clock PeriodtSCLK = Serial Port Clock PeriodCR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)SR = Serial Port/Core Clock Ratio (wide range,
determined by �CLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning-
ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con-
sequently, it is not meaningful to add parameters to derive
longer times.
See Figure32 under Test Conditions for voltage reference
levels.
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris-
tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris-
tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
ADSP-21160M
Clock Input
Reset
Table 4. Clock InputFigure 10. Clock Input
Table 5. ResetApplies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than100ms while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
afterreset.
Figure 11. Reset
Interrupts
Timer
Table 6. InterruptsOnly required for IRQx recognition in the following cycle.Applies only if tSIR and tHIR requirements are not met.
Figure 12. Interrupts
Table 7. TimerFigure 13. Timer
ADSP-21160M
Flags
Table 8. Flags Flag inputs meeting these setup and hold times for instruction cycle N will affect conditional instructions in instruction cycle N+2.
Figure 14. Flags
Memory Read—Bus MasterUse these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 9. Memory Read—Bus MasterW = (number of wait states specified in WAIT register) � tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).Data Delay/Setup: User must meet tDAD, tDRLD, or tSDS.The falling edge of MSx, BMS is referenced.Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.Data Hold: User must meet tHDA or tHDRH in asynchronous access mode. See Example System Hold Time Calculation on page44 for the calculation of
hold times given capacitive and dc loads.ACK Delay/Setup: User must meet tDAAK, tDSAK, or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
ADSP-21160M
Memory Write—Bus MasterUse these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 10. Memory Write—Bus MasterW = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1ACK Delay/Setup: User must meet tDAAK or tDSAK or tSAKC for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).The falling edge of MSx, BMS is referenced.
3Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.See Example System Hold Time Calculation on page44 for calculation of hold times given capacitive and dc loads.
Figure 16. Memory Write—Bus Master
ADSP-21160M
Synchronous Read/Write—Bus MasterUse these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for
accessing a slave ADSP-21160M (in multiprocessor
memory space). These synchronous switching characteris-
tics are also valid during asynchronous memory reads and
writes except where noted (see Memory Read—Bus Master
on page19 and Memory Write—Bus Master on page20).
When accessing a slave ADSP-21160M, these switching
characteristics must meet the slave’s timing requirements
for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on page24). The slave
ADSP-21160M must also meet these (bus master) timing
requirements for data and acknowledge setup and hold
times.
Table 11. Synchronous Read/Write—Bus MasterNote that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.Applies to broadcast write, master precharge of ACK.Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.
Figure 17. Synchronous Read/Write—Bus Master
ADSP-21160M
Synchronous Read/Write—Bus SlaveUse these specifications for ADSP-21160M bus master
accesses of a slave’s IOP registers or internal memory (in
multiprocessor memory space). The bus master must meet
these (bus slave) timing requirements.
Table 12. Synchronous Read/Write—Bus Slave
Figure 18. Synchronous Read/Write—Bus Slave
ADSP-21160M
Multiprocessor Bus Request and Host Bus RequestUse these specifications for passing of bus mastership
between multiprocessing ADSP-21160Ms (BRx) or a host
processor (HBR, HBG).
Table 13. Multiprocessor Bus Request and Host Bus RequestOnly required for recognition in the current cycle.(O/D) = open drain, (A/D) = active drive.
