ADSP-21065LKCA264 ,DSP MicrocomputeraDSP MicrocomputerADSP-21065LSUMMARY SDRAM Controller for Glueless Interface to Low CostHigh Perfor ..
ADSP-21065LKCA-264 ,DSP MicrocomputerFEATURESParallel Computations66 MIPS, 198 MFLOPS Peak, 132 MFLOPS SustainedSingle-Cycle Multiply an ..
ADSP-21065LKS-240 ,DSP MicrocomputerGENERAL DESCRIPTIONADSP-21065LThe ADSP-21065L is a powerful member of the SHARC#1CSCLOCKCLKINBOOTfa ..
ADSP21065LKS-240 ,DSP Microcomputerfeatures an enhanced Super Harvard Archi-FIR Filter (per Tap) 15 ns 1tecture in which the data memo ..
ADSP21065LKS-240. ,DSP MicrocomputeraDSP MicrocomputerADSP-21065LSUMMARY SDRAM Controller for Glueless Interface to Low CostHigh Perfor ..
ADSP-21065LKS-264 ,DSP Microcomputerfeatures an enhanced Super Harvard Archi-FIR Filter (per Tap) 15 ns 1tecture in which the data memo ..
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
AM2370N , N-Channel 100V (D-S) MOSFET
ADSP-21065LCS-240-ADSP21065LCS-240-ADSP-21065LKCA-240-ADSP-21065LKCA264-ADSP-21065LKCA-264-ADSP-21065LKS-240-ADSP21065LKS-240-ADSP21065LKS-240.-ADSP-21065LKS-264
DSP Microcomputer
REV. B
DSP Microcomputer
SUMMARY
High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and
Industrial Applications
Super Harvard Architecture Computer (SHARC®)
Four Independent Buses for Dual Data, Instruction,
and I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory and Integrated I/O
Peripheral2S Support, for Eight Simultaneous Receive and Trans-
mit Channels
KEY FEATURES
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
Two External Port, DMA Channels and Eight Serial
Port, DMA Channels
SDRAM Controller for Glueless Interface to Low Cost
External Memory (@ 66 MHz)
64M Words External Address Range
12 Programmable I/O Pins and Two Timers with Event
Capture Options
Code-Compatible with ADSP-2106x Family
208-Lead MQFP or 196-Ball Mini-BGA Package
3.3 Volt Operation
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision IEEE
Floating-PointData Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation
1024-Point Complex FFT Benchmark: 0.274 ms (18,221
Cycles)Figure 1.Functional Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
ADSP-21065L
544 Kbits Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable in Combinations of 16-, 32-, 48-Bit Data and
Program Words in Block 0 and Block 1
DMA Controller
Ten DMA Channels—Two Dedicated to the External Port
and Eight Dedicated to the Serial Ports
Background DMA Transfers at up to 66 MHz, in Parallel
with Full Speed Processor Execution
Performs Transfers Between:
Internal RAM and Host
Internal RAM and Serial Ports
Internal RAM and Master or Slave SHARC
Internal RAM and External Memory or I/O Devices
External Memory and External Devices
Host Processor Interface
Efficient Interface to 8-, 16-, and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21065L IOP Registers
Multiprocessing
Distributed On-Chip Bus Arbitration for Glueless, Parallel
Bus Connect Between Two ADSP-21065Ls Plus Host
132 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Independent Transmit and Receive Functions
Programmable 3-Bit to 32-Bit Serial Word Width2S Support Allowing Eight Transmit and Eight Receive
Channels
Glueless Interface to Industry Standard Codecs
TDM Multichannel Mode with �-Law/A-Law Hardware
Companding
Multichannel Signaling Protocol
GENERAL DESCRIPTIONThe ADSP-21065L is a powerful member of the SHARC
family of 32-bit processors optimized for cost sensitive appli-
cations. The SHARC—Super Harvard Architecture—offers the
highest levels of performance and memory integration of any
32-bit DSP in the industry—they are also the only DSP in the
industry that offer both fixed and floating-point capabilities,
without compromising precision or performance.
Fabricated in a high speed, low power CMOS process, 0.35µm
technology, the ADSP-21065L offers the highest performance
by a 32-bit DSP—66 MIPS (198 MFLOPS). With its on-chip
instruction cache, the processor can execute every instruction in
a single cycle. Table I lists the performance benchmarks for the
ADSP-21065L.
The ADSP-21065L SHARC combines a floating-point DSP
core with integrated, on-chip system features, including a
544Kbit SRAM memory, host processor interface, DMA con-
troller, SDRAM controller, and enhanced serial ports.
Figure 1 shows a block diagram of the ADSP-21065L, illustrat-
ing the following architectural features:
Computation Units (ALU, Multiplier, and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Timers with Event Capture Modes
On-Chip, dual-ported SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and SDRAM Interface
DMA Controller
Enhanced Serial Ports
JTAG Test Access Port
Table I. Performance BenchmarksFIR Filter (per Tap)
IIR Filter (per Biquad)
Divide Y/X
Inverse Square Root (1/√x)
ADSP-21000 FAMILY CORE ARCHITECTUREThe ADSP-21065L is code and function compatible with the
ADSP-21060/ADSP-21061/ADSP-21062. The ADSP-21065L
includes the following architectural features of the SHARC
family core.
Figure 2.ADSP-21065L Single-Processor System
Independent, Parallel Computation UnitsThe arithmetic/logic unit (ALU), multiplier, and shifter all
perform single-cycle instructions. The three units are arranged
in parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier
operations. These computation units support IEEE 32-bit
single-precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Data Register FileA general-purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two OperandsThe ADSP-21065L features an enhanced Super Harvard Archi-
tecture in which the data memory (DM) bus transfers data and
the program memory (PM) bus transfers both instructions and
data (see Figure 1). With its separate program and data memory
buses, and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction CacheThe ADSP-21065L includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions that
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
ADSP-21065Lstructures required in digital signal processing, and are com-
monly used in digital filters and Fourier transforms. The
ADSP-21065L’s two DAGs contain sufficient registers to allow
the creation of up to 32 circular buffers (16 primary register
sets, 16 secondary). The DAGs automatically handle address
pointer wraparound, reducing overhead, increasing perfor-
mance, and simplifying implementation. Circular buffers can
start and end at any memory location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21065L can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21065L FEATURESThe ADSP-21065L is designed to achieve the highest system
throughput to enable maximum system performance. It can be
clocked by either a crystal or a TTL-compatible clock signal.
The ADSP-21065L uses an input clock with a frequency equal
to half the instruction rate—a 33 MHz input clock yields ans processor cycle (which is equivalent to 66 MHz). Inter-
faces on the ADSP-21065L operate as shown below. Hereafter
in this document, 1x = input clock frequency, and 2x = processor’s
instruction rate.
The following clock operation ratings are based on 1x = 33MHz
(instruction rate/core = 66 MHz):
SDRAM66 MHz
External SRAM33 MHz
Serial Ports33 MHz
Multiprocessing33 MHz
Host (Asynchronous)33 MHz
Augmenting the ADSP-21000 family core, the ADSP-21065L
adds the following architectural features:
Dual-Ported On-Chip MemoryThe ADSP-21065L contains 544 Kbits of on-chip SRAM,
organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has
256 Kbits. Bank 0 is configured with 9 columns of 2K × 16 bits,
and Bank 1 is configured with 8 columns of 2K × 16 bits. Each
memory block is dual-ported for single-cycle, independent ac-
cesses by the core processor and I/O processor or DMA control-
ler. The dual-ported memory and separate on-chip buses allow
two data transfers from the core and one from I/O, all in a
single cycle (see Figure 4 for the ADSP-21065L Memory Map).
On the ADSP-21065L, the memory can be configured as a
maximum of 16K words of 32-bit data, 34K words for 16-bit
data, 10K words of 48-bit instructions (and 40-bit data) or
combinations of different word sizes up to 544 Kbits. All the
memory can be accessed as 16-bit, 32-bit or 48-bit.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores in-
structions and data, using the PM bus for transfers. Using the
DM and PM busses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
Off-Chip Memory and Peripherals InterfaceThe ADSP-21065L’s external port provides the processor’s
interface to off-chip memory and peripherals. The 64M words,
off-chip address space is included in the ADSP-21065L’s uni-
fied address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 24-bit ad-
dress bus, four memory selects, and a single 32-bit data bus.
The on-chip Super Harvard Architecture provides three bus
performance, while the off-chip unified address space gives
flexibility to the designer.
SDRAM InterfaceThe SDRAM interface enables the ADSP-21065L to transfer
data to and from synchronous DRAM (SDRAM) at 2x clock
frequency. The synchronous approach coupled with 2x clock
frequency supports data transfer at a high throughput—up to
220 Mbytes/sec.
The SDRAM interface provides a glueless interface with stan-
dard SDRAMs—16 Mb, 64 Mb, and 128 Mb—and includes
options to support additional buffers between the ADSP-21065L
and SDRAM. The SDRAM interface is extremely flexible and
provides capability for connecting SDRAMs to any one of the
ADSP-21065L’s four external memory banks.
Systems with several SDRAM devices connected in parallel may
require buffering to meet overall system timing requirements.
The ADSP-21065L supports pipelining of the address and
control signals to enable such buffering between itself and mul-
tiple SDRAM devices.
Host Processor InterfaceThe ADSP-21065L’s host interface provides easy connection to
standard microprocessor buses—8-, 16-, and 32-bit—requiring
little additional hardware. Supporting asynchronous transfers at
speeds up to 1x clock frequency, the host interface is accessed
through the ADSP-21065L’s external port. Two channels of
DMA are available for the host interface; code and data trans-
fers are accomplished with low software overhead.
The host processor requests the ADSP-21065L’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
IOP registers of the ADSP-21065L and can access the DMA
channel setup and mailbox registers. Vector interrupt support
enables efficient execution of host commands.
DMA ControllerThe ADSP-21065L’s on-chip DMA controller allows zero-
overhead, nonintrusive data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21065L’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21065L’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-, or
I/O transfers). Programs can be downloaded to the ADSP-
21065L using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/Grant
lines (DMAR1-2, DMAG1-2). Other DMA features include inter-
rupt generation on completion of DMA transfers and DMA
chaining for automatically linked DMA transfers.
Serial PortsThe ADSP-21065L features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
1x clock frequency, providing each with a maximum data rate of
33 Mbit/s. Each serial port has a primary and a secondary set of
transmit and receive channels. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports supports
three operation modes: DSP serial port mode, I2S mode (an
interface commonly used by audio codecs), and TDM (Time
Division Multiplex) multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with selectable word lengths of 3 bits to
32 bits. They offer selectable synchronization and transmit
modes and optional µ-law or A-law companding. Serial port
clocks and frame syncs can be internally or externally generated.
The serial ports also include keyword and keymask features to
enhance interprocessor communication.
Programmable Timers and General Purpose I/O PortsThe ADSP-21065L has two independent timer blocks, each of
which performs two functions—Pulsewidth Generation and
Pulse Count and Capture.
In Pulsewidth Generation mode, the ADSP-21065L can gener-
ate a modulated waveform with an arbitrary pulsewidth within
a maximum period of 71.5 secs.
In Pulse Counter mode, the ADSP-21065L can measure either
the high or low pulsewidth and the period of an input waveform.
The ADSP-21065L also contains twelve programmable, general
purpose I/O pins that can function as either input or output. As
output, these pins can signal peripheral devices; as input, these
pins can provide the test for conditional branching.
Program BootingThe internal memory of the ADSP-21065L can be booted at
system power-up from an 8-bit EPROM, a host processor, or
external memory. Selection of the boot source is controlled by
the BMS (Boot Memory Select) and BSEL (EPROM Boot)
pins. Either 8-, 16-, or 32-bit host processors can be used for
booting. For details, see the descriptions of the BMS and BSEL
pins in the Pin Descriptions section of this data sheet.
MultiprocessingThe ADSP-21065L offers powerful features tailored to multi-
processing DSP systems. The unified address space allows
direct interprocessor accesses of both ADSP-21065L’s IOP
registers. Distributed bus arbitration logic is included on-chip
for simple, glueless connection of systems containing a maxi-
mum of two ADSP-21065Ls and a host processor. Master pro-
cessor changeover incurs only one cycle of overhead. Bus lock
DEVELOPMENT TOOLSThe ADSP-21065L is supported with a complete set of software
and hardware development tools, including the EZ-ICE® In-
Circuit Emulator and development software.
The same EZ-ICE hardware that you use for the ADSP-21060/
ADSP-21062 also fully emulates the ADSP-21065L.
Both the SHARC Development Tools family and the VisualDSP®
integrated project management and debugging environment
support the ADSP-21065L. The VisualDSP project manage-
ment environment enables you to develop and debug an appli-
cation from within a single integrated program.
The SHARC Development Tools include an easy to use Assem-
bler that is based on an algebraic syntax; an Assembly library/
librarian; a linker; a loader; a cycle-accurate, instruction-level
simulator; a C compiler; and a C run-time library that includes
DSP and mathematical functions.
Debugging both C and Assembly programs with the Visual DSP
debugger, you can:View Mixed C and Assembly CodeInsert Break PointsSet Watch PointsTrace Bus ActivityProfile Program ExecutionFill and Dump MemoryCreate Custom Debugger Windows
The Visual IDE enables you to define and manage multiuser
projects. Its dialog boxes and property pages enable you to
configure and manage all of the SHARC Development Tools.
This capability enables you to:Control how the development tools process inputs and gen-
erate outputs.Maintain a one-to-one correspondence with the tool’s com-
mand line switches.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21065L processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
Additional InformationFor detailed information on the ADSP-21065L instruction set
and architecture, see the ADSP-21065L SHARC User’s Manual,
Third Edition, and the ADSP-21065L SHARC Technical Reference.
ADSP-21065LFigure 3.Multiprocessing System
PIN DESCRIPTIONSADSP-21065L pin definitions are listed below. Inputs identified as synchronous (S) must meet timing requirements with respect to
CLKIN (or with respect to TCK for TMS, TDI). Inputs identified as asynchronous (A) can be asserted asynchronously to CLKIN
(or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND, except for ADDR23-0, DATA31-0, FLAG11-0, SW, and inputs that have
internal pull-up or pull-down resistors (CPA, ACK, DTxX, DRxX, TCLKx, RCLKx, TMS, and TDI)—these pins can be left float-
ing. These pins have a logic-level hold circuit that prevents the input from floating internally.
I = InputS = SynchronousP = Power Supply(O/D) = Open Drain
O = OutputA = AsynchronousG = Ground(A/D) = Active Drive
T = Three-state (when SBTS is asserted, or when the ADSP-2106x is a bus slave)
DATA31-0
MS3-0
ACK
SBTS
IRQ2-0
ADSP-21065LDMAG2
BR2-1
ID1-0
CPA (O/D)
CLKIN
RESET
TCK
TMS
TDI
TDO
TRST
EMU (O/D)
BMSTR
CAS
RAS
SDWE
ADSP-21065LXTAL
PWM_EVENT1-0
CLOCK SIGNALSThe ADSP-21065L can use an external clock or a crystal. See
CLKIN pin description. You can configure the ADSP-21065L
to use its internal clock generator by connecting the necessary
components to CLKIN and XTAL. You can use either a crystal
operating in the fundamental mode or a crystal operating at an
overtone. Figure 4 shows the component connections used for a
crystal operating in fundamental mode, and Figure 5 shows
the component connections used for a crystal operating at an
overtone.
CLKIN
XTAL
SUGGESTED COMPONENTS FOR 30 MHz OPERATION:
ECLIPTEK EC2SM-33-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-33-30.000M (THRU-HOLE PACKAGE)
C1 = 33pF
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS.Figure 4.30 MHz Operation (Fundamental Mode Crystal)
CLKINXTAL
SUGGESTED COMPONENTS FOR 30MHz OPERATION:
ECLIPTEK EC2SM-T-30.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK ECT-30.000M (THRU-HOLE PACKAGE)
C1 = 18pF
C2 = 27pF
C3 = 75pF
L1 = 3300nH
RS = SEE NOTE.
NOTE: C1, C2, C3, RS AND L1 ARE SPECIFIC TO CRYSTAL SPECIFIED
FOR X1. CONTACT MANUFACTURER FOR DETAILS.Figure 5.30 MHz Operation (3rd Overtone Crystal)
TARGET BOARD CONNECTOR FOR EZ-ICE PROBEThe ADSP-2106x EZ-ICE emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and con-
trol the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK, TRST,
TDI, TDO, EMU and GND signals be made accessible on the
target system via a 14-pin connector (a 2 row x 7 pin strip header)
such as that shown in Figure 6. The EZ-ICE probe plugs di-
rectly onto this connector for chip-on-board emulation. You
must add this connector to your target board design if you,
intend to use the ADSP-2106x EZ-ICE.
The total trace length between the EZ-ICE connector and the
furthest device sharing the EZ-ICE JTAG pins should be lim-
ited to 15 inches maximum for guaranteed operation. This
restriction on length must include EZ-ICE JTAG signals, which
are routed to one or more 2106x devices or to a combination of
2106xs and other JTAG devices on the chain.
The 14-pin, 2-row pin strip header is keyed at the Pin 3 loca-
tion—you must remove Pin 3 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. Pin strip headers are available
from vendors such as 3M, McKenzie and Samtec.
Figure 6.Target Board Connector for ADSP-2106x EZ-ICE
(JTAG Header)
The BTMS, BTCK, BTRST and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If you are not
going to use the test access port for board testing, tie BTRST
to GND and tie or pull-up BTCK to VDD. The TRST pin must
be asserted after power-up (through BTRST on the connector)
or held low for proper operation of the ADSP-2106x. None of
the Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE
probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op-
erations such as starting, stopping, and single-stepping two
ADSP-21065Ls in a synchronous manner. If you do not need
these operations to occur synchronously on the two processors,
simply tie Pin 4 of the EZ-ICE header to ground.
For systems which use the internal clock generator and an exter-
nal discrete crystal, do not directly connect the CLKIN pin to
the JTAG probe. This will load the oscillator circuit and possi-
bly cause it to fail to oscillate. Instead the JTAG probe’s
CLKIN can be driven by the XTAL pin through a high imped-
ance buffer.
If synchronous multiprocessor operations are needed and CLKIN
is connected, clock skew between multiple ADSP-2106x proces-
sors and the CLKIN pin on the EZ-ICE header must be mini-
mal. If the skew is too large, synchronous operations may be off
by one cycle between processors. For synchronous multiproces-
sor operation TCK, TMS, CLKIN and EMU should be treated
as critical signals in terms of skew, and should be laid out as
short as possible on your board.
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For Complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User’s Guide and Reference.
ADSP-21065L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONSVIH
NOTE
See Environmental Conditions for information on thermal specifications.
ELECTRICAL CHARACTERISTICSVOL
IIH
IILP
IOZH
IOZLS
IOZLA
IOZLAR
NOTESApplies to input and bidirectional pins: DATA31-0, ADDR23-0, BSEL, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG11-0, HBG, CS, DMAR1, DMAR2, BR2-1, ID2-0,
RPBA, CPA, TFS0, TFS1, RFS0, RFS1, BMS, TMS, TDI, TCK, HBR, DR0A, DR1A, DR0B, DR1B, TCLK0, TCLK1, RCLK0, RCLK1, RESET, TRST,
PWM_EVENT0, PWM_EVENT1, RAS, CAS, SDWE, SDCKE.Applies to input pin CLKIN.Applies to output and bidirectional pins: DATA31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, HBG, REDY, DMAG1, DMAG2, BR2-1, CPA, TCLK0,
TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, DT0A, DT1A, DT0B, DT1B, XTAL, BMS, TDO, EMU, BMSTR, PWM_EVENT0, PWM_EVENT1,
RAS, CAS, DQM, SDWE, SDCLK0, SDCLK1, SDCKE, SDA10.See Output Drive Currents for typical drive current capabilities.Applies to input pins: ACK, SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID1-0, BSEL, CLKIN, RESET, TCK (Note that ACK is pulled up internally with 2kΩ
during reset in a multiprocessor system, when ID1-0 = 01 and another ADSP-21065L is not requesting bus mastership.)Applies to input pins with internal pull-ups: DR0A, DR1A, DR0B, DR1B, TRST, TMS, TDI.Applies to three-statable pins: DATA31-0, ADDR23-0, MS3-0, RD, WR, SW, ACK, FLAG11-0, REDY, HBG, DMAG1, DMAG2, BMS, TDO, RAS, CAS, DQM,
SDWE, SDCLK0, SDCLK1, SDCKE, SDA10 and EMU (Note that ACK is pulled up internally with2kΩ during reset in a multiprocessor system, when ID1-0 =
01 and another ADSP-21065L is not requesting bus mastership).Applies to three-statable pins with internal pull-ups: DT0A, DT1A, DT0B, DT1B, TCLK0, TCLK1, RCLK0, RCLK1.Applies to CPA pin.Applies to ACK pin when pulled up.Applies to ACK pin when keeper latch enabled.Guaranteed but not tested.Applies to all signal pins.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . .–0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . .130°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . .+280°C
*Stresses greater than those listed above may cause permanent damage to the device.
These are stress ratings only; functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of this specifica-
tion is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
POWER DISSIPATION ADSP-21065LThese specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note SHARC Power Dissipation Measurements.
Specifications are based on the following operating scenarios:
Table II.Internal Current MeasurementsTo estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE16 × IDDIDLE16 = POWER CONSUMPTION
Table III.Internal Current Measurement ScenariosNOTESThe test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.IDDINHIGH is a composite average based on a range of high activity code.IDDINLOW is a composite average based on a range of low activity code.IDLE denotes ADSP-21065L state during execution of IDLE instruction.IDLE16 denotes ADSP-21065L state during execution of IDLE16 instruction.
TIMING SPECIFICATIONS
General NotesTwo speed grades of the ADSP-21065L are offered, 60 MHz and 66 MHz instruction rates. The specifications shown are based on a
CLKIN frequency of 30 MHz (tCK = 33.3 ns). The DT derating allows specifications at other CLKIN frequencies (within the min–
max range of the tCK specification; see Clock Input below). DT is the difference between the actual CLKIN period and a CLKIN
period of 33.3 ns:
DT = (tCK – 33.3)/32
Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addi-
tion or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical varia-
tions and worst cases. Consequently, you cannot meaningfully add parameters to derive longer times.
See Figure 27 in Equivalent Device Loading for AC Measurements (Includes All Fixtures) for voltage reference levels.
ADSP-21065LSwitching Characteristics specify how the processor changes its signals. You have no control over this timing—circuitry external to the
processor must be designed for compatibility with these signal characteristics. Switching characteristics tell you what the processor
will do in a given circumstance. You can also use switching characteristics to ensure that any timing requirement of a device con-
nected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read opera-
tion. Timing requirements guarantee that the processor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
tCKL
tCKH
Figure 7.Clock Input
NOTESApplies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 3000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after
reset.
Figure 8.Reset
tHIR
NOTES
1Only required for IRQx recognition in the following cycle.
Figure 9.Interrupts
tHTI
Switching Characteristics:
tDTEX
tHFI
Switching Characteristics:
tDFO
NOTEFlag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
Figure 10.Flags
ADSP-21065L
Memory Read—Bus MasterUse these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char-
acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim-
ing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
tHDRH
tDAAK
tDARL
tRW
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTESData Delay/Setup: User must meet tDAD or to tDRLD or synchronous specification tSSDATI.The falling edge of MSx, SW, BMS, are referenced.ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).
Figure 11.Memory Read—Bus Master
Memory Write—Bus MasterUse these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the ADSP-21065L is the bus master when accessing external memory space. These switching char-
acteristics also apply for bus master synchronous read/write timing (see Synchronous Read/Write—Bus Master below). If these tim-
ing requirements are met, the synchronous read/write timing can be ignored (and vice versa). An exception to this is the ACK pin
timing requirements as described in the note below.
tDAWL
tWW
tDDWH
tDATRWH
tWWR
tDDWR
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTESACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).The falling edge of MSx, SW, and BMS is referenced.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Figure 12.Memory Write—Bus Master
ADSP-21065L
Synchronous Read/Write—Bus MasterUse these specifications for interfacing to external memory systems that require CLKIN-relative timing or for accessing a slave
ADSP-21065L (in multiprocessor memory space). These synchronous switching characteristics are also valid during asynchronous
memory reads and writes (see Memory Read—Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-21065L, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The slave ADSP-21065L must also meet these (bus master) timing require-
ments for data and acknowledge setup and hold times.
tHSDATI
tDAAK
tHACK
Switching Characteristics:
tDADRO
tDRWL
tDDATO
tDATTR
tDBM
W = (number of wait states specified in WAIT register) × tCK.
NOTESData Hold: User must meet tHDA or tHDRH or synchronous specification tHDATI. See system hold time calculation under test conditions for the calculation of hold
times given capacitive and dc loads.ACK is not sampled on external memory accesses that use the Internal wait state mode. For the first CLKIN cycle of a new external memory access, ACK must be
valid by tDAAK or tDSAK or synchronous specification tSACKC for wait state modes External, Either, or Both (Both, if the internal wait state is zero). For the second and
subsequent cycles of a wait stated external memory access, synchronous specifications tSACKC and tHACKC must be met for wait state modes External, Either, or Both
(Both, after internal wait states have completed).See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Figure 13.Synchronous Read/Write—Bus Master
ADSP-21065L
Synchronous Read/Write—Bus SlaveUse these specifications for ADSP-21065L bus master accesses of a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave) timing requirements.
tHADRI
tSRWLI
tHRWLI
tRWHPI
tSDATWH
Switching Characteristics:
tSDDATO
tDATTR
tDACK
NOTEStSRWLI is specified when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min) = 17.5 + 18 DT.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
For two ADSP-21065Ls to communicate synchronously as master and slave, certain master and slave specification combinations
must be satisfied. Do not compare specification values directly to calculate master/slave clock skew margins for those specifications
listed below. The following table shows the appropriate clock skew margin.
Table IV.Bus Master to Slave Skew Margins
Figure 14.Synchronous Read/Write—Bus Slave
ADSP-21065L
Multiprocessor Bus Request and Host Bus RequestUse these specifications for passing of bus mastership between multiprocessing ADSP-21065Ls (BRx) or a host processor (HBR,HBG).
tSHBRI
tSHBGI
tHHBGI
tSBRI
Switching Characteristics:
tDHBGO
tHHBGO
tDBRO
tHBRO
tDCPAO
tTRCPA
tDRDYCS
tTRDYHG
NOTESFor first asynchronous access after HBR and CS asserted, ADDR23-0 must be a nonMMS value 1/2 tCK before RD or WR goes low or by tHBGRCSV after HBG goes
low. This is easily accomplished by driving an upper address signal high when HBG is asserted. See the Host Processor Control of the ADSP-21065L section of the
ADSP-21065L SHARC User’s Manual, Second Edition.Only required for recognition in the current cycle.CPA assertion must meet the setup to CLKIN; deassertion does not need to meet the setup to CLKIN.(O/D) = open drain, (A/D) = active drive.
