ADSP-21065L ,Low-Cost SHARC, 60 MHz, 180 MFLOPS, 3.3v, Floating PointFEATURES60 MIPS, 180 MFLOPS peak, 120 MFLOPS sustained DMA ControllerperformanceTen DMA channelstw ..
ADSP-21065LCS-240 ,DSP Microcomputerfeatures, including aCONTROL RAS RASCAS CAS544 Kbit SRAM memory, host processor interface, DMA con- ..
ADSP21065LCS-240 ,DSP MicrocomputerFEATURESParallel Computations66 MIPS, 198 MFLOPS Peak, 132 MFLOPS SustainedSingle-Cycle Multiply an ..
ADSP-21065LKCA-240 ,DSP MicrocomputerGENERAL DESCRIPTIONADSP-21065LThe ADSP-21065L is a powerful member of the SHARC#1CSCLOCKCLKINBOOTfa ..
ADSP-21065LKCA264 ,DSP MicrocomputeraDSP MicrocomputerADSP-21065LSUMMARY SDRAM Controller for Glueless Interface to Low CostHigh Perfor ..
ADSP-21065LKCA-264 ,DSP MicrocomputerFEATURESParallel Computations66 MIPS, 198 MFLOPS Peak, 132 MFLOPS SustainedSingle-Cycle Multiply an ..
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
ADSP-21065L
Low-Cost SHARC, 60 MHz, 180 MFLOPS, 3.3v, Floating Point
FEATURES60 MIPS, 180 MFLOPS peak, 120 MFLOPS sustained DMA ControllerperformanceTen DMA channelstwo dedicated to the external port and User-configurable 544K bits on-chip SRAM memory eight dedicated to the serial portsTwo external port, DMA channels and eight serial port, DMA Background DMA transfers at up to 60 MHz, in parallel with channels full speed processor executionSDRAM controller for glueless interface to low cost external Performs transfers between:memory (@ 60 MHz)Internal RAM and host64M words external address rangeInternal RAM and serial ports12 programmable I/O pins and two timers with event capture Internal RAM and master or slave SHARCoptionsInternal RAM and external memory or I/O devicesCode-compatible with ADSP-2106x familyExternal memory and external devices208-lead MQFP packageSnPb (tin, lead) terminal finishHost Processor Interface3.3 Volt operationEfficient interface to 8-, 16-, and 32-bit microprocessorsHost can directly read/write ADSP-21065L-EP IOP registersFlexible Data Formats and 40-Bit Extended Precision32-bit single-precision and 40-bit extended-precision IEEE Multiprocessingfloating-point data formatsDistributed on-chip bus arbitration for glueless, parallel32-bit fixed-point data format, integer and fractional, with bus connect between two ADSP-21065L-EP processors dual 80-bit accumulatorsplus host120M bytes/sec transfer rate over parallel bus Parallel ComputationsSingle-cycle multiply and ALU operations in parallel with Serial Portsdual memory read/writes and instruction fetchIndependent transmit and receive functionsMultiply with add and subtract for accelerated FFT butterfly Programmable 3-bit to 32-bit serial word widthcomputation2I S support allowing eight transmit and eight receive 1024-point complex FFT benchmark: 301 µs (18,221 cycles)channelsGlueless interface to industry standard codecs544K bits Configurable On-Chip SRAMTDM multichannel mode with µ-law/A-law hardwareDual-ported for independent access by core processor and compandingDMAMultichannel signaling protocolConfigurable in combinations of 16-, 32-, 48-bit data and pro-gram words in Block 0 and Block 1Rev. A | Page 2 of 14 | September 2012Enhanced Product ADSP-21065L-EP
