ADSP-21062LKB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTIONprocessing system is shown in Figure 3.The ADSP-21062 SHARC—Super Harvard Archit ..
ADSP-21062LKB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilySPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17Figure 17. Multiprocessor Bus Reques ..
ADSP21062LKB-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 8. Clock Input . . . ..
ADSP-21062LKS-133 ,ADSP-2106x SHARC DSP Microcomputer FamilySPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17Figure 17. Multiprocessor Bus Reques ..
ADSP-21062LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTIONprocessing system is shown in Figure 3.The ADSP-21062 SHARC—Super Harvard Archit ..
ADSP21062LKS-160 ,ADSP-2106x SHARC DSP Microcomputer Familyfeatures:SComputation Units (ALU, Multiplier and Shifter) with aShared Data Register FileData Addre ..
AM2130-10DC , 1024x8 Dual-Port Static Random-Access Memories
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
ADSP-21062CS-160-ADSP21062CS-160-ADSP-21062KS133-ADSP-21062KS-133-ADSP21062KS-133-ADSP-21062KS160-ADSP-21062KS-160-ADSP21062KS-160-ADSP-21062LAB-160-ADSP-21062LCS160-ADSP-21062LCS-160-ADSP21062LCS-160-ADSP-21062LKB-160-ADSP21062LKB-160-ADSP-21062LKS-133-ADSP-21062LKS-160-ADSP2106
ADSP-2106x SHARC DSP Microcomputer Family
REV.C
ADSP-2106x SHARC®
DSP Microcomputer Family
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
2 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop SetupSHARC is a registered trademark of Analog Devices, Inc.
Figure 1.ADSP-21062/ADSP-21062L Block Diagram
ADSP-21062/ADSP-21062L
DMA Controller
10 DMA Channels for Transfers Between ADSP-21062
Internal Memory and External Memory, External
Peripherals, Host Processor, Serial Ports, or Link
Ports
Background DMA Transfers at 40 MHz, in Parallel with
Full-Speed Processor Execution
Host Processor Interface to 16- and 32-Bit Microprocessors
Host Can Directly Read/Write ADSP-21062 Internal
Memory
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up to Six ADSP-21062s Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
240 Mbytes/s Transfer Rate Over Parallel Bus
240 Mbytes/s Transfer Rate Over Link Ports
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports with Com-
panding Hardware
Independent Transmit and Receive Functions
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21062/ADSP-21062L FEATURES . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
TARGET BOARD CONNECTOR FOR EZ-ICE®
PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RECOMMENDED OPERATING CONDITIONS . . . . . . 13
ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 13
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 17
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 20
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 21
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 24
Multiprocessor Bus Request and Host Bus Request . . . . . 26
Asynchronous Read/Write—Host to ADSP-21062 . . . . . . 28
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Link Ports:1 × CLK Speed Operation . . . . . . . . . . . . . . 33
Link Ports:2 × CLK Speed Operation . . . . . . . . . . . . . . 34
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 39
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 40
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 43
225 Ball Plastic Ball Grid Array (PBGA)
Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .44
225 Ball Plastic Ball Grid Array (PBGA)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PACKAGE DIMENSIONS, 225-Ball PBGA . . . . . . . . . . . 46
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 47
PACKAGE DIMENSIONS, 240-Lead Metric MQFP . . . 48
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
FiguresFigure 1.ADSP-21062/ADSP-21062L Block Diagram . . . . 1
Figure 2.ADSP-21062 System . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3.Shared Memory Multiprocessing System . . . . . . . . 6
Figure 4.ADSP-21062/ADSP-21062L Memory Map . . . . . 7
Figure 5.Target Board Connector For ADSP-2106x
Figure 7.JTAG Clocktree for Multiple ADSP-2106x
Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8.Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9.Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10.Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11.Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 12.Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Memory Read—Bus Master . . . . . . . . . . . . . . . . 20
Figure 14.Memory Write—Bus Master . . . . . . . . . . . . . . . 21
Figure 15.Synchronous Read/Write—Bus Master . . . . . . . 23
Figure 16.Synchronous Read/Write—Bus Slave . . . . . . . . . 25
Figure 17.Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18a.Synchronous REDY Timing . . . . . . . . . . . . . . 28
Figure 18b.Asynchronous Read/Write—Host to
ADSP-21062 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19a.Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Figure 19b.Three-State Timing (Host Transition Cycle) . .30
Figure 20.DMA Handshake Timing . . . . . . . . . . . . . . . . . 32
Figure 21.Link Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22.Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23.External Late Frame Sync . . . . . . . . . . . . . . . . . 38
Figure 24.IEEE 11499.1 JTAG Test Access Port . . . . . . . 39
Figure 25.Output Enable/Disable . . . . . . . . . . . . . . . . . . . 41
Figure 26.Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 27.Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . 41
Figure 28.ADSP-21062 Typical Drive Currents
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 29.Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . 42
Figure 30.Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 31.Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . . 42
Figure 32.ADSP-21062 Typical Drive Currents
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 33.Typical Output Rise Time (10%–90% VDD)
vs. Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . 42
Figure 34.Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . 43
including a 2 Mbit SRAM memory (4 Mbit on the ADSP-21060),
host processor interface, DMA controller, serial ports and
link port and parallel bus connectivity for glueless DSP
multiprocessing.
Figure 1 shows a block diagram of the ADSP-21062, illustrating
the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port and Multiprocessor Interface
DMA Controller
Serial Ports and Link Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I.ADSP-21062/ADSP-21062L Benchmarks (@ 40 MHz)
GENERAL NOTEThis data sheet represents production released specifications for
the ADSP-21062 (5V) and ADSP-21062L (3.3V) processors,
for both 33 MHz and 40 MHz speed grades. The product name
“ADSP-21062” is used throughout this data sheet to represent
all devices, except where expressly noted.
GENERAL DESCRIPTIONThe ADSP-21062 SHARC—Super Harvard Architecture
Computer—is a signal processing microcomputer that offers new
capabilities and levels of performance. The ADSP-21062
SHARCs are 32-bit processors optimized for high performance
DSP applications. The ADSP-21062 builds on the ADSP-21000
DSP core to form a complete system-on-a-chip, adding a dual-
ported on-chip SRAM and integrated I/O peripherals supported
by a dedicated I/O bus.
Fabricated in a high speed, low power CMOS process, the
ADSP-21062 has a 25 ns instruction cycle time and operates
at 40MIPS. With its on-chip instruction cache, the processor
can execute every instruction in a single cycle. Table I shows
performance benchmarks for the ADSP-21062.
The ADSP-21062 SHARC represents a new standard of inte-
gration for signal computers, combining a high performance
floating-point DSP core with integrated, on-chip system features
ADSP-21062/ADSP-21062L
ADSP-21000 FAMILY CORE ARCHITECTUREThe ADSP-21062 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21062 processors
are code- and function-compatible with the ADSP-21020.
Independent, Parallel Computation UnitsThe arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier opera-
tions. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point, and 32-bit fixed-point data formats.
Figure 2.ADSP-21062 System
Data Register FileA general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two OperandsThe ADSP-21062 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction CacheThe ADSP-21062 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular BuffersThe ADSP-21062’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The two DAGs of the
ADSP-21062 contain sufficient registers to allow the creation of
up to 32 circular buffers (16 primary register sets, 16 secondary).
The DAGs automatically handle address pointer wraparound,
reducing overhead, increasing performance and simplifying
implementation. Circular buffers can start and end at any
memory location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21062 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21062/ADSP-21062L FEATURESAugmenting the ADSP-21000 family core, the ADSP-21062
adds the following architectural features:
Dual-Ported On-Chip MemoryThe ADSP-21062 contains two megabits of on-chip SRAM,
organized as two blocks of 1 Mbits each, which can be config-
ured for different combinations of code and data storage. Each
memory block is dual-ported for single-cycle, independent ac-
cesses by the core processor and I/O processor or DMA control-
ler. The dual-ported memory and separate on-chip buses allow
two data transfers from the core and one from I/O, all in a single
cycle.
On the ADSP-21062, the memory can be configured as a maxi-
mum of 64K words of 32-bit data, 128K words of 16-bit data,
40K words of 48-bit instructions (or 40-bit data), or combina-
tions of different word sizes up to two megabits. All of the
memory can be accessed as 16-bit, 32-bit or 48-bit words.
A 16-bit floating-point storage format is supported, which effec-
tively doubles the amount of data that may be stored on-chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores
instructions and data, using the PM bus for transfers. Using the
DM bus and PM bus in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21062’s external port.
include interrupt generation upon completion of DMA trans-
fers and DMA chaining for automatic linked DMA transfers.
Serial PortsThe ADSP-21062 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from 3 bits to
32 bits. They offer selectable synchronization and transmit
modes as well as optional µ-law or A-law companding. Serial
port clocks and frame syncs can be internally or externally
generated.
MultiprocessingThe ADSP-21062 offers powerful features tailored to multi-
processor DSP systems. The unified address space (see
Figure 4) allows direct interprocessor accesses of each ADSP-
21062’s internal memory. Distributed bus arbitration logic is
included on-chip for simple, glueless connection of systems
containing up to six ADSP-21062s and a host processor. Master
processor changeover incurs only one cycle of overhead. Bus
arbitration is selectable as either fixed or rotating priority. Bus lock
allows indivisible read-modify-write sequences for semaphores. A
vector interrupt is provided for interprocessor commands. Maxi-
mum throughput for interprocessor data transfer is 240 Mbytes/s
over the link ports or external port. Broadcast writes allow simulta-
neous transmission of data to all ADSP-21062s and can be used
to implement reflective semaphores.
Link PortsThe ADSP-21062 features six 4-bit link ports that provide addi-
tional I/O capabilities. The link ports can be clocked twice per
cycle, allowing each to transfer eight bits of data per cycle. Link
port I/O is especially useful for point-to-point interprocessor
communication in multiprocessing systems.
The link ports can operate independently and simultaneously,
with a maximum data throughput of 240 Mbytes/s. Link port
data is packed into 32- or 48-bit words, and can be directly read
by the core processor or DMA-transferred to on-chip memory.
Each link port has its own double-buffered input and output
registers. Clock/acknowledge handshaking controls link port
transfers. Transfers are programmable as either transmit or
receive.
Program BootingThe internal memory of the ADSP-21062 can be booted at
system power-up from either an 8-bit EPROM, a host proces-
sor, or through one of the link ports. Selection of the boot
source is controlled by the BMS (Boot Memory Select),
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.
32-bit and 16-bit host processors can be used for booting.
Off-Chip Memory and Peripherals InterfaceThe ADSP-21062’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21062’s unified
address space. The separate on-chip buses—for PM addresses,
PM data, DM addresses, DM data, I/O addresses and I/O
data—are multiplexed at the external port to create an external
system bus with a single 32-bit address bus and a single 48-bit
(or 32-bit) data bus.
Addressing of external memory devices is facilitated by on-chip
decoding of high-order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21062
provides programmable memory wait states and external
memory acknowledge controls to allow interfacing to DRAM
and peripherals with variable access, hold and disable time
requirements.
Host Processor InterfaceThe ADSP-21062’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21062’s exter-
nal port and is memory-mapped into the unified address space.
Four channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21062’s external bus
with the host bus request (HBR), host bus grant (HBG), and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21062, and can access the DMA
channel setup and mailbox registers. Vector interrupt support is
provided for efficient execution of host commands.
DMA ControllerThe ADSP-21062’s on-chip DMA controller allows zero-
overhead data transfers without processor intervention. The
DMA controller operates independently and invisibly to the
processor core, allowing DMA operations to occur while the
core is simultaneously executing its program instructions.
DMA transfers can occur between the ADSP-21062’s internal
memory and either external memory, external peripherals or a
host processor. DMA transfers can also occur between the
ADSP-21062’s internal memory and its serial ports or link
ports. DMA transfers between external memory and external
peripheral devices are another option. External bus packing to
16-, 32-, or 48-bit words is performed during DMA transfers.
Ten channels of DMA are available on the ADSP-21062—two
via the link ports, four via the serial ports, and four via the
processor’s external port (for either host processor, other
ADSP-21062s, memory or I/O transfers). Four additional
link port DMA channels are shared with serial port 1 and the
external port. Programs can be downloaded to the ADSP-
21062 using DMA transfers. Asynchronous off-chip peripher-
als can control two DMA channels using DMA Request/
Grant lines (DMAR1-2, DMAG1-2). Other DMA features
ADSP-21062/ADSP-21062LFigure 3.Shared Memory Multiprocessing System
Figure 4.ADSP-21062/ADSP-21062L Memory Map
DEVELOPMENT TOOLSThe ADSP-21062 is supported with a complete set of software
and hardware development tools, including an EZ-ICE In-
Circuit Emulator, EZ-LAB® development board, EZ-KIT, and
development software. The EZ-LAB contains an evaluation board
with an ADSP-21062 (5 V) processor and provides a serial connec-
tion to your PC. The SHARC EZ-KIT combines the ADSP-
21000 Family Development Software for the PC and the
EZ-LAB ADSP-21062’s Development Board in one package.
The EZ-KIT contains in addition to the EZ-LAB development
board, an optimizing compiler, assembler, instruction level simu-
lator, run-time libraries, diagnostic utilities and a complete set
of example programs.
The same EZ-ICE hardware can be used for the ADSP-21060/
ADSP-21061, to fully emulate the ADSP-21062, with the excep-
tion of displaying and modifying the two new SPORTS registers.
The emulator will not display these two registers, but your
code can use them.
Analog Devices’ ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
an Assembly Library/Librarian, a Linker, an Instruction-level
Simulator, an ANSI C optimizing Compiler, the CBug™ C
Source-Level Debugger, and a C Runtime Library including
DSP and mathematical functions. The Optimizing Compiler
includes Numerical C extensions based on the work of the
ANSI Numerical C Extensions Group. Numerical C provides
extensions to the C language for array selection, vector math
dimensioned arrays. The ADSP-21000 Family Development
Software is available for both the PC and Sun platforms.
The ADSP-21062 EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-21062 processor to monitor
and control the target board processor during emulation. The
EZ-ICE provides full-speed emulation, allowing inspection and
modification of memory, registers, and processor stacks. Nonintru-
sive in-circuit emulation is assured by the use of the processor’s
JTAG interface—the emulator does not affect target system
loading or timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware & Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office, distributor or
the Literature Center.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards, multiprocessor
SHARC VME boards, and daughter card modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third party software
tools include an Ada compiler, DSP libraries, operating systems,
and block diagram design tools.
ADDITIONAL INFORMATION
ADSP-21062/ADSP-21062L
PIN FUNCTION DESCRIPTIONSADSP-21062 pin definitions are listed below. All pins are iden-
tical on the ADSP-21062 and ADSP-21062L. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31-0, DATA47-0, FLAG3-0, SW, and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
DRx, TCLKx, RCLKx, LxDAT3-0, LxCLK, LxACK, TMS
and TDI)—these pins can be left floating. These pins have a
logic-level hold circuit that prevents the input from floating
internally.
A = AsynchronousG = GroundI = Input
O = OutputP = Power SupplyS = Synchronous
(A/D) = Active Drive(O/D) = Open Drain
T = Three-State (when SBTS is asserted, or when the
ADSP-21062 is a bus slave)
ADSP-21062/ADSP-21062LICSA
VDD
GND
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie, and Samtec.
The BTMS, BTCK, BTRST, and BTDI signals are provided so
that the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the BXXX pins and the XXX pins as shown in
Figure 5. If you are not going to use the test access port for
board testing, tie BTRST to GND and tie or pull up BTCK to
VDD. The TRST pin must be asserted after power-up (through
BTRST on the connector) or held low for proper operation of
the ADSP-2106x. None of the BXXX pins (Pins 5, 7, 9, 11) are
connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as follows:
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBEThe ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and
control the target board processor during emulation. The EZ-
ICE probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made acces-
sible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pin should be limited to 15
inches maximum for guaranteed operation. This length restric-
tion must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP-
2106x devices and other JTAG devices on the chain.
Figure 5.Target Board Connector For ADSP-2106x
EZ-ICE Emulator (Jumpers in Place)
Figure 6.JTAG Scan Path Connections for Multiple ADSP-2106x Systems
ADSP-21062/ADSP-21062LFigure 7.JTAG Clocktree for Multiple ADSP-2106x Systems
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping, and single-stepping mul-
tiple ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP-
21062 processors and the CLKIN pin on the EZ-ICE header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For syn-
chronous multiprocessor operation TCK, TMS, CLKIN and
EMU should be treated as critical signals in terms of skew,
and should be laid out as short as possible on your board. If
TCK, TMS, and CLKIN are driving a large number of ADSP-
21062s (more than eight) in your system, then treat them as a
“clock tree” using multiple drivers to minimize skew. (See
Figure 7 “JTAG Clock Tree” and “Clock Distribution” in the
“High Frequency Design Considerations” section of the ADSP-
2106x User’s Manual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termi-
nation on TCK and TMS. TDI, TDO, EMU and TRST are
not critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
ADSP-21062–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)NOTESApplies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)NOTESApplies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.See “Output Drive Currents” for typical drive current capabilities.Applies to input pins:ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI.Applies to three-statable pins:DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 is
not requesting bus mastership.)Applies to three-statable pins with internal pull-ups:DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to CPA pin.Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21062L is not requesting bus mastership).Applies to three-statable pins with internal pull-downs:LxDAT3-0, LxCLK, LxACK.Applies to ACK pin when keeper latch enabled.Applies to all signal pins.Guaranteed but not tested.
Specifications subject to change without notice.
ADSP-21062/ADSP-21062L
ADSP-21062/ADSP-21062L
POWER DISSIPATION ADSP-21062 (5 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
NOTESThe test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.Idle denotes ADSP-21062L state during execution of IDLE instruction.
ADSP-21062L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)NOTESApplies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)NOTESApplies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.See “Output Drive Currents” for typical drive current capabilities.Applies to input pins:ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK.Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI.Applies to three-statable pins:DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-21062 is
not requesting bus mastership.)Applies to three-statable pins with internal pull-ups:DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to CPA pin.Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21062L is not requesting bus mastership).Applies to three-statable pins with internal pull-downs:LxDAT3-0, LxCLK, LxACK.Applies to ACK pin when keeper latch enabled.Applies to all signal pins.Guaranteed but not tested.
Specifications subject to change without notice.
ADSP-21062/ADSP-21062L
ADSP-21062/ADSP-21062L
POWER DISSIPATION ADSP-21062L (3.3 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE = power consumption
NOTESThe test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.IDDINHIGH is a composite average based on a range of high activity code. IDDINLOW is a composite average based on a range of low activity code.Idle denotes ADSP-21062L state during execution of IDLE instruction.
ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-21062 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
TIMING SPECIFICATIONS
GENERAL NOTESTwo speed grades of the ADSP-21062 will be offered, 40 MHz
and 33.3 MHz. The specifications shown are based on a
CLKIN frequency of 40 MHz (tCK = 25 ns). The DT derating
allows specifications at other CLKIN frequencies (within the
min–max range of the tCK specification; see Clock Input below).
DT is the difference between the actual CLKIN period and a
CLKIN period of 25 ns:
DT = tCK – 25ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
For voltage reference levels, see Figure 27 under Test Conditions.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use
switching characteristics to ensure that any timing requirement
of a device connected to the processor (such as memory) is
satisfied.
Timing Requirements apply to signals that are controlled by cir-
cuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS (3.3 V DEVICE)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ADSP-21062/ADSP-21062LFigure 8.Clock Input
NOTESApplies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET
is low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).Only required if multiple ADSP-21062s must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-21062s communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
Figure 9.Reset
NOTESOnly required for IRQx recognition in the following cycle.Applies only if tSIR and tHIR requirements are not met.
Figure 11.Timer
NOTEFlag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
Figure 12.Flags
ADSP-21062/ADSP-21062LtHDRH
tDAAK
tDARL
tRW
tSADADC
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTESData Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI.Data Hold: User must meet tHDA or tHDRH or synchronous spec tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).The falling edge of MSx, SW, BMS is referenced.
Figure 13.Memory Read—Bus Master
Memory Read—Bus MasterUse these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write – Bus Master below). If
these timing requirements are met, the synchronous read/write
timing can be ignored (and vice versa).
Memory Write—Bus MasterUse these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21062 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write–Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
W = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTESACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).The falling edge of MSx, SW, BMS is referenced.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Figure 14.Memory Write—Bus Master
ADSP-21062/ADSP-21062LtHSDATI
tDAAK
tSACKC
Switching Characteristics:
tDADRO
tHADRO
tDPGC
tDRDO
tDWRO
tDRWL
tSDDATO
tDATTR
tADRCK
W = (number of Wait states specified in WAIT register) × tCK.
NOTESThe falling edge of MSx, SW, BMS is referenced.ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Synchronous Read/Write—Bus MasterUse these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21062 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-21062, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21062 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Figure 15.Synchronous Read/Write—Bus Master
ADSP-21062/ADSP-21062LtRWHPI
tSDATWH
NOTEStSRWLI (min) = 9.5 + 5DT/16 when Multiprocessor Memory Space Wait State (MMSWS bit in WAIT register) is disabled; when MMSWS is enabled, tSRWLI (min)
= 4 + DT/8.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.tDACKAD is true only if the address and SW inputs have setup times (before CLKIN) greater than 10 + DT/8 and less than 19 + 3DT/4. If the address and SW inputs have
setup times greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK
regardless of the state of MMSWS or strobes. A slave will three-state ACK every cycle with tACKTR.
Synchronous Read/Write—Bus SlaveUse these specifications for ADSP-21062 bus master accesses of
a slave’s IOP registers or internal memory (in multiprocessor
memory space). The bus master must meet these (bus slave)
timing requirements.
