ADSP-21061-LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyGENERAL DESCRIPTIONInterval TimerThe ADSP-21061 is a member of the powerful SHARC family1 Mbit On-C ..
ADSP-21061LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)50 MIPS, 20 ns Instruction Rate, S ..
ADSP-21061LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyCHARACTERISTICS (3.3 V) . . . . . . . . . . 16 Figure 16. Synchronous Read/Write—Bus Slave . . . . ..
ADSP21061LKS-160 ,ADSP-2106x SHARC DSP Microcomputer FamilyCHARACTERISTICS (5 V) . . . . . . . . . . . 14 Figure 13. Memory Read—Bus Master . . . . . . . . . ..
ADSP-21061LKS-176 ,ADSP-2106x SHARC DSP Microcomputer FamilyFEATURES1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)50 MIPS, 20 ns Instruction Rate, S ..
ADSP-21061LKSZ-160 , Commercial Grade SHARC DSP Microcomputer
AM2130-10DC , 1024x8 Dual-Port Static Random-Access Memories
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2130-12PC , 1024x8 Dual-Port Static Random-Access Memories
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2336N , N-Channel 30-V (D-S) MOSFET
AM2361P , P-Channel 60-V (D-S) MOSFET
ADSP-21061KS-133-ADSP-21061KS-160-ADSP21061KS-160-ADSP-21061KS-200-ADSP21061KS-200-ADSP-21061LKB-160-ADSP-21061-LKS-160-ADSP-21061LKS-160-ADSP21061LKS-160-ADSP-21061LKS-176
ADSP-2106x SHARC DSP Microcomputer Family
REV.B
ADSP-2106x SHARC®
DSP Microcomputer Family
Pin-Compatible with ADSP-21060 (4 Mbit) and
ADSP-21062 (2 Mbit)
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)
1 Megabit Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable as 32K Words Data Memory (32-Bit), 16K
Words Program Memory (48-Bit) or Combinations of
Both Up to 1 Mbit
Off-Chip Memory Interfacing
4-Gigawords Addressable (32-Bit Address)
Programmable Wait State Generation, Page-Mode DRAM
Support
SUMMARY
High Performance Signal Computer for Speech, Sound,
Graphics and Imaging Applications
Super Harvard Architecture Computer (SHARC)—
Four Independent Buses for Dual Data, Instructions,
and I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU and Shifter
1 Megabit On-Chip SRAM Memory and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)SHARC is a registered trademark of Analog Devices, Inc.
Figure 1.ADSP-21061/ADSP-21061L Block Diagram
ADSP-21061/ADSP-21061L
DMA Controller
6 DMA Channels
Background DMA Transfers at 50 MHz, in Parallel with
Full-Speed Processor Execution
Performs Transfers Between ADSP-21061 Internal Memory
and External Memory, External Peripherals, Host
Processor, or Serial Ports
Host Processor Interface
Efficient Interface to 16- and 32-Bit Microprocessors
Host can Directly Read/Write ADSP-21061 Internal Memory
Multiprocessing
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of Up To Six ADSP-21061s Plus Host
300 Mbytes/s Transfer Rate Over Parallel Bus
Serial Ports
Two 40 Mbit/s Synchronous Serial Ports
Independent Transmit and Receive Functions
3- to 32-Bit Data Word Width�-Law/A-Law Hardware Companding
TDM Multichannel Mode
Multichannel Signaling Protocol
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 3
ADSP-21000 FAMILY CORE ARCHITECTURE . . . . . . . 4
ADSP-21061 FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . 4
DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . 8
ADDITIONAL INFORMATION . . . . . . . . . . . . . . . . . . . . .8
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TARGET BOARD CONNECTOR FOR EZ-ICE
®PROBE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
RECOMMENDED OPERATING CONDITIONS (5 V) . 14
ELECTRICAL CHARACTERISTICS (5 V) . . . . . . . . . . . 14
POWER DISSIPATION ADSP-21061 (5 V) . . . . . . . . . . . .15
RECOMMENDED OPERATING CONDITIONS (3.3 V) 16
ELECTRICAL CHARACTERISTICS (3.3 V) . . . . . . . . . . 16
POWER DISSIPATION ADSP-21061L (3.3 V) . . . . . . . . .17
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . .18
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . 18
Memory Read—Bus Master . . . . . . . . . . . . . . . . . . . . . . . 21
Memory Write—Bus Master . . . . . . . . . . . . . . . . . . . . . . 22
Synchronous Read/Write—Bus Master . . . . . . . . . . . . . . 23
Synchronous Read/Write—Bus Slave . . . . . . . . . . . . . . . . 25
Multiprocessor Bus Request and Host Bus Request . . . . . 26
Asynchronous Read/Write—Host to ADSP-21061 . . . . . . 28
Three-State Timing—Bus Master, Bus Slave,
HBR, SBTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
DMA Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
JTAG Test Access Port and Emulation . . . . . . . . . . . . . . . 37
OUTPUT DRIVE CURRENTS . . . . . . . . . . . . . . . . . . . . . 38
POWER DISSIPATION . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TEST CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ENVIRONMENTAL CONDITIONS . . . . . . . . . . . . . . . . 41
240-LEAD METRIC MQFP PIN CONFIGURATIONS . . 42
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 43, 44
ADSP-21061L 225-Ball Plastic Ball Grid Array (PBGA)
Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
225-Ball Plastic Ball Grid Array (PBGA) Package Pinout . . . . . 46
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . .47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
FIGURESFigure 1.ADSP-21061/ADSP-21061L Block Diagram . . . . 1
Figure 2.ADSP-21061/ADSP-21061L System . . . . . . . . . . . 4
ADSP-21061L EZ-ICE Emulator (Jumpers in Place) . . . 12
Figure 6.JTAG Scan Path Connections for Multiple
ADSP-21061/ADSP-21061L Systems . . . . . . . . . . . . . . . 12
Figure 7.JTAG Clocktree for Multiple ADSP-21061/
ADSP-21061L Systems . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8.Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 9.Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10.Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12.Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 13.Memory Read—Bus Master . . . . . . . . . . . . . . . . 21
Figure 14.Memory Write—Bus Master . . . . . . . . . . . . . . . 22
Figure 15.Synchronous Read/Write—Bus Master . . . . . . . 24
Figure 16.Synchronous Read/Write—Bus Slave . . . . . . . . . 25
Figure 17.Multiprocessor Bus Request and Host Bus
Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18a.Synchronous REDY Timing . . . . . . . . . . . . . .28
Figure 18b.Asynchronous Read/Write—Host to
ADSP-21061/ADSP-21061L . . . . . . . . . . . . . . . . . . . . . . 29
Figure 19a.Three-State Timing (Bus Transition Cycle,
SBTS Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Figure 19b.Three-State Timing (Host Transition Cycle) . .31
Figure 20.DMA Handshake Timing . . . . . . . . . . . . . . . . . 33
Figure 21.Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22.External Late Frame Sync . . . . . . . . . . . . . . . . . 36
Figure 23.JTAG Test Access Port and Emulation . . . . . . . 37
Figure 24.Output Enable/Disable . . . . . . . . . . . . . . . . . . . 39
Figure 25.Equivalent Device Loading for AC Measurements
(Includes All Fixtures) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26.Voltage Reference Levels for AC Measurements
(Except Output Enable/Disable) . . . . . . . . . . . . . . . . . . . . 39
Figure 27.ADSP-2106x Typical Drive Currents
(VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 28.Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . .40
Figure 29.Typical Output Rise Time (0.8 V–2.0 V) vs. Load
Capacitance (VDD = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 30.Typical Output Delay or Hold vs. Load Capacitance
(at Maximum Case Temperature) (VDD = 5 V) . . . . . . . .40
Figure 31.ADSP-2106x Typical Drive Currents
(VDD = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Figure 32.Typical Output Rise Time (10%–90% VDD) vs.
Load Capacitance (VDD = 3.3 V) . . . . . . . . . . . . . . . . . . .40
Figure 1 shows a block diagram of the ADSP-21061/ADSP-
21061L, illustrating the following architectural features:
Computation Units (ALU, Multiplier and Shifter) with a
Shared Data Register File
Data Address Generators (DAG1, DAG2)
Program Sequencer with Instruction Cache
Interval Timer
1 Mbit On-Chip SRAM
External Port for Interfacing to Off-Chip Memory and
Peripherals
Host Port & Multiprocessor Interface
DMA Controller
Serial Ports
JTAG Test Access Port
Figure 2 shows a typical single-processor system. A multi-
processing system is shown in Figure 3.
Table I.ADSP-21061/ADSP-21061L Benchmarks (@ 50 MHz)
GENERAL NOTEThis data sheet represents production released specifications
for the ADSP-21061 5 V and ADSP-21061L 3.3 V proces-
sors. ADSP-21061 is used throughout this data sheet to refer to
both devices unless expressly noted.
GENERAL DESCRIPTIONThe ADSP-21061 is a member of the powerful SHARC family
of floating point processors. The SHARC—Super Harvard
Architecture Computer—are signal processing microcomputers
that offer new capabilities and levels of integration and perfor-
mance. The ADSP-21061 is a 32-bit processor optimized for
high performance DSP applications. The ADSP-21061 com-
bines the ADSP-21000 DSP core with a dual-ported on-chip
SRAM and an I/O processor with a dedicated I/O bus to form a
complete system-in-a-chip.
Fabricated in a high-speed, low-power CMOS process, the
ADSP-21061 has a 20 ns instruction cycle time operating at up
to 50 MIPS. With its on-chip instruction cache, the processor can
execute every instruction in a single cycle. Table I shows perfor-
mance benchmarks for the ADSP-21061/ADSP-21061L.
The ADSP-21061 SHARC combines a high-performance float-
ing-point DSP core with integrated, on-chip system features,
including a 1 Mbit SRAM memory, host processor interface,
DMA controller, serial ports and parallel bus connectivity for
glueless DSP multiprocessing.
ADSP-21061/ADSP-21061L
ADSP-21000 FAMILY CORE ARCHITECTUREThe ADSP-21061 includes the following architectural features
of the ADSP-21000 family core. The ADSP-21061 is code and
function compatible with the ADSP-21060/ADSP-21062 and
the ADSP-21020.
Independent, Parallel Computation UnitsThe arithmetic/logic unit (ALU), multiplier and shifter all per-
form single-cycle instructions. The three units are arranged in
parallel, maximizing computational throughput. Single multi-
function instructions execute parallel ALU and multiplier op-
erations. These computation units support IEEE 32-bit single-
precision floating-point, extended precision 40-bit floating-
point and 32-bit fixed-point data formats.
Figure 2.ADSP-21061/ADSP-21061L System
Data Register FileA general purpose data register file is used for transferring data
between the computation units and the data buses, and for
storing intermediate results. This 10-port, 32-register (16 pri-
mary, 16 secondary) register file, combined with the ADSP-
21000 Harvard architecture, allows unconstrained data flow
between computation units and internal memory.
Single-Cycle Fetch of Instruction and Two OperandsThe ADSP-21061 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1). With its separate program and data memory
buses and on-chip instruction cache, the processor can simulta-
neously fetch two operands and an instruction (from the cache),
all in a single cycle.
Instruction CacheThe ADSP-21061 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and two
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
allows full-speed execution of core, looped operations such as
digital filter multiply-accumulates and FFT butterfly processing.
Data Address Generators with Hardware Circular BuffersThe ADSP-21061’s two data address generators (DAGs) imple-
ment circular data buffers in hardware. Circular buffers allow
efficient programming of delay lines and other data structures
required in digital signal processing, and are commonly used in
digital filters and Fourier transforms. The ADSP-21061 two
DAGs contain sufficient registers to allow the creation of up to
32 circular buffers (16 primary register sets, 16 secondary). The
DAGs automatically handle address pointer wraparound, reduc-
ing overhead, increasing performance and simplifying imple-
mentation. Circular buffers can start and end at any memory
location.
Flexible Instruction SetThe 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the ADSP-
21061 can conditionally execute a multiply, an add, a subtract
and a branch, all in a single instruction.
ADSP-21061 FEATURESAugmenting the ADSP-21000 family core, the ADSP-21061
adds the following architectural features:
Dual-Ported On-Chip MemoryThe ADSP-21061 contains 1 megabit of on-chip SRAM, orga-
nized as two banks of 0.5 Mbits each. Each bank has eight 16-
bit columns with 4K 16-bit words per column. Each memory
block is dual-ported for single-cycle, independent accesses by
the core processor and I/O processor or DMA controller. The
dual-ported memory and separate on-chip buses allow two data
transfers from the core and one from I/O, all in a single cycle
(see Figure 4 for the ADSP-21061 Memory Map).
On the ADSP-21061, the memory can be configured as a maxi-
mum of 32K words of 32-bit data, 64K words for 16-bit data,
16K words of 48-bit instructions (and 40-bit data) or combina-
tions of different word sizes up to 1 megabit. All the memory
can be accessed as 16-bit, 32-bit or 48-bit.
A 16-bit floating-point storage format is supported that effec-
tively doubles the amount of data that may be stored on chip.
Conversion between the 32-bit floating-point and 16-bit floating-
point formats is done in a single instruction.
While each memory block can store combinations of code and
data, accesses are most efficient when one block stores data,
using the DM bus for transfers, and the other block stores in-
structions and data, using the PM bus for transfers. Using the
DM and PM buses in this way, with one dedicated to each
memory block, assures single-cycle execution with two data
transfers. In this case, the instruction must be available in the
cache. Single-cycle execution is also maintained when one of the
data operands is transferred to or from off-chip, via the ADSP-
21061’s external port.
Off-Chip Memory and Peripherals InterfaceThe ADSP-21061’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 32-bit address
bus and a single 48-bit (or 32-bit) data bus. The on-chip
Super Harvard Architecture provides three-bus performance,
while the off-chip unified address space gives flexibility to the
designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to DRAM and peripher-
als with variable access, hold and disable time requirements.
Host Processor InterfaceThe ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter-
nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG) and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the
DMA channel setup and mailbox registers. Vector interrupt
support is provided for efficient execution of host commands.
DMA ControllerThe ADSP-21061’s on-chip DMA controller allows zero-
overhead, nonintrusive data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-
or 48-bit words is performed during DMA transfers.
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR1-2, DMAG1-2). Other DMA features include interrupt
generation upon completion of DMA transfers and DMA chain-
ing for automatic linked DMA transfers.
Serial PortsThe ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from three
bits to 32 bits. They offer selectable synchronization and trans-
mit modes as well as optional µ-law or A-law companding.
Serial port clocks and frame syncs can be internally or externally
generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
MultiprocessingThe ADSP-21061 offers powerful features tailored to multipro-
cessing DSP systems. The unified address space allows direct
interprocessor accesses of each ADSP-21061’s internal memory.
Distributed bus arbitration logic is included on-chip for simple,
glueless connection of systems containing up to six ADSP-21061s
and a host processor. Master processor changeover incurs only
one cycle of overhead. Bus arbitration is selectable as either
fixed or rotating priority. Bus lock allows indivisible read-modify-
write sequences for semaphores. A vector interrupt is provided
for interprocessor commands. Maximum throughput for inter-
processor data transfer is 500 Mbytes/sec over the external port.
Broadcast writes allow simultaneous transmission of data to
all ADSP-21061s and can be used to implement reflective
semaphores.
Program BootingThe internal memory of the ADSP-21061 can be booted at
system power-up from either an 8-bit EPROM or a host proces-
sor. Selection of the boot source is controlled by the BMS (Boot
Memory Select), EBOOT (EPROM Boot), and LBOOT (Host
Boot) pins. 32-bit and 16-bit host processors can be used for
booting. See the BMS pin in the Pin Function Descriptions
section of this data sheet.
ADSP-21061/ADSP-21061LFigure 3.Multiprocessing System
Figure 4.ADSP-21061/ADSP-21061L Memory Map
ADSP-21061/ADSP-21061L
Porting Code from ADSP-21060 or ADSP-21062 to the
ADSP-21061The ADSP-21061 is pin compatible with the ADSP-21060/
ADSP-21061/ADSP-21062 processors. The ADSP-21061 pins
that correspond to the Link Port pins of the ADSP-21060/
ADSP-21062 are no-connects.
The ADSP-21061 is object code compatible with the ADSP-
21060/ADSP-21062 except for the following functional
changes:
The ADSP-21061 memory is organized into two blocks
with eight columns that are 4K deep per block. The
ADSP-21060/ADSP-21062 memory has 16 columns per block.
Link port functions are not available.
Handshake external port DMA pins DMAR2 and DMAG2
are assigned to external port DMA Channel 6 instead of
Channel 8.
2-D DMA capability of the SPORT is not available.
The modify registers in SPORT DMA are not programmable.
On the ADSP-21061, Block 0 starts at the beginning of internal
memory, normal word address 0x0002 0000. Block 1 starts at
the end of Block 0, with contiguous addresses. The remaining
addresses in internal memory are divided into blocks that alias
into Block 1. This allows any code or data stored in Block 1 on
the ADSP-21062 to retain the same addresses on the ADSP-
21061—these addresses will alias into the actual Block 1 of each
processor.
If you develop your application using the ADSP-21062, but will
migrate to the ADSP-21061, use only the first eight columns of
each memory bank. Limit your application to 8K of instructions
or up to 16K of data in each bank of the ADSP-21062, or any
combinations of instructions or data that does not exceed the
memory bank.
DEVELOPMENT TOOLSThe ADSP-21061 is supported with a complete set of software
and hardware development tools, including an EZ-ICE In-
Circuit Emulator, EZ-Kit Lite, and development software. The
SHARC EZ-Kit Lite (ADDS-2106x-EZ-Lite) is a complete low
cost package for DSP evaluation and prototyping. The EZ-Kit
Lite contains an evaluation board with an ADSP-21061 (5 V)
processor and provides a serial connection to your PC. The EZ-
Kit Lite also includes an optimizing compiler, assembler, in-
struction level simulator, run-time libraries, diagnostic utilities
and a complete set of example programs.
The same EZ-ICE hardware can be used for the ADSP-21060/
ADSP-21062, to fully emulate the ADSP-21061, with the excep-
tion of displaying and modifying the two new SPORTS
registers. The emulator will not display these two registers,
but your code can use them.
Analog Devices ADSP-21000 Family Development Software
includes an easy to use Assembler based on an algebraic syntax,
Assembly Library/Librarian, Linker, instruction-level Simulator,
an ANSI C optimizing Compiler, the CBUG™ C Source—
Level Debugger and a C Runtime Library including DSP and
mathematical functions. The Optimizing Compiler includes
Numerical C extensions based on the work of the ANSI Nu-
merical C Extensions Group. Numerical C provides extensions
to the C language for array selections, vector math operations,
complex data types, circular pointers and variably dimensioned
arrays. The ADSP-21000 Family Development Software is
available for both the PC and Sun platforms.
The EZ-ICE Emulator uses the IEEE 1149.1 JTAG test access
port of the ADSP-21061 processor to monitor and control the
target board processor during emulation. The EZ-ICE provides
full-speed emulation, allowing inspection and modification of
memory, registers, and processor stacks. Nonintrusive in-circuit
emulation is assured by the use of the processor’s JTAG inter-
face—the emulator does not affect target system loading or
timing.
Further details and ordering information are available in the
ADSP-21000 Family Hardware and Software Development Tools
data sheet (ADDS-210xx-TOOLS). This data sheet can be
requested from any Analog Devices sales office or distributor.
In addition to the software and hardware development tools
available from Analog Devices, third parties provide a wide
range of tools supporting the SHARC processor family. Hard-
ware tools include SHARC PC plug-in cards multiprocessor
SHARC VME boards, and daughter and modules with multiple
SHARCs and additional memory. These modules are based on
the SHARCPAC™ module specification. Third Party software
tools include an Ada compiler, DSP libraries, operating systems
and block diagram design tools.
ADDITIONAL INFORMATIONThis data sheet provides a general overview of the ADSP-21061
architecture and functionality. For detailed information on the
ADSP-21000 Family core architecture and instruction set, refer to
the ADSP-2106x SHARC User’s Manual, Second Edition.
PIN DESCRIPTIONSADSP-21061 pin definitions are listed below. Inputs identified
as synchronous (S) must meet timing requirements with respect
to CLKIN (or with respect to TCK for TMS, TDI). Inputs
identified as asynchronous (A) can be asserted asynchronously
to CLKIN (or to TCK for TRST).
Unused inputs should be tied or pulled to IVDD or IGND,
except for ADDR31-0, DATA47-0, FLAG3-0, SW and inputs that
have internal pull-up or pull-down resistors (CPA, ACK, DTx,
DRx, TCLKx, RCLKx, TMS and TDI)—these pins can be left
floating. These pins have a logic-level hold circuit that prevents
the input from floating internally.
I = InputS = SynchronousP = Power Supply
(O/D) = Open DrainO = OutputA = Asynchronous
G = Ground(A/D) = Active Drive
T = Three-State (when SBTS is asserted, or when the
ADSP-2106x is a bus slave)
PIN FUNCTION DESCRIPTIONSDATA47-0
MS3-0
PAGE
ADRCLK
ACK
ADSP-21061/ADSP-21061LHBG
REDY (O/D)
DMAR1
DMAR2
DMAG1
DMAG2
BR6-1
ADSP-21061/ADSP-21061LThe 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie BTRST to GND
and tie or pull BTCK up to VDD. The TRST pin must be
asserted after power-up (through BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
TARGET BOARD CONNECTOR FOR EZ-ICE PROBEThe ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made acces-
sible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pins should be limited to 15
inches maximum for guaranteed operation. This length restric-
tion must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP-
2106x devices and other JTAG devices on the chain.
Figure 5.Target Board Connector For ADSP-21061/ADSP-
21061L EZ-ICE Emulator (Jumpers in Place)
Figure 6.JTAG Scan Path Connections for Multiple ADSP-21061/ADSP-21061L Systems
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform op-
erations such as starting, stopping and single-stepping multiple
ADSP-2106x in a synchronous manner. If you do not need these
operations to occur synchronously on the multiple processors,
simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP-
21061x processors and the CLKIN pin on the EZ-ICE header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For syn-
chronous multiprocessor operation TCK, TMS, CLKIN and
EMU should be treated as critical signals in terms of skew, and
should be laid out as short as possible on your board. If TCK,
TMS and CLKIN are driving a large number of ADSP-2106x
(more than eight) in your system, then treat them as a clock tree
using multiple drivers to minimize skew. (See Figure 7, JTAG
Clock Tree, and Clock Distribution in the High Frequency
Design Considerations section of the ADSP-2106x User’s
Manual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termina-
tion on TCK and TMS. TDI, TDO, EMU and TRST are not
critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the ADSP-
21000 Family JTAG EZ-ICE User’s Guide and Reference.
Figure 7.JTAG Clocktree for Multiple ADSP-21061/ADSP-21061L Systems
ADSP-21061/ADSP-21061L
ADSP-21061–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (5 V)TCASE
VIH2
NOTESApplies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (5 V)VOL
NOTESApplies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.See Output Drive Currents section for typical drive current capabilities.Applies to input pins:ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up
internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI.Applies to three-statable pins:DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is
not requesting bus mastership.)Applies to three-statable pins with internal pull-ups:DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to CPA pin.Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21061x is not requesting bus mastership).Applies to three-statable pins with internal pull-downs:LxDAT3-0, LxCLK, LxACK.Applies to ACK pin when keeper latch enabled.Applies to all signal pins.Guaranteed but not tested.
Specifications subject to change without notice.
POWER DISSIPATION ADSP-21061 (5 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation, see
the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE + %IDLE16 × IDDIDLE16 = power consumption
NOTESThe test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.IDDINHIGH is a composite average based on a range of high activity code.IDDINLOW is a composite average based on a range of low activity code.Idle denotes ADSP-21061 state during execution of IDLE instruction.Idle16 denotes ADSP-21061 state during execution of IDLE16 instruction.
ADSP-21061/ADSP-21061L
ADSP-21061L–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS (3.3 V)TCASE
VIH2
NOTESApplies to input and bidirectional pins: DATA47-0, ADDR31-0, RD, WR, SW, ACK, SBTS, IRQ2-0, FLAG3-0, HBG, CS, DMAR1, DMAR2, BR6-1, ID2-0, RPBA,
CPA, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, EBOOT, LBOOT, BMS, TMS, TDI, TCK, HBR, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to input pins: CLKIN, RESET, TRST.
ELECTRICAL CHARACTERISTICS (3.3 V)VOL
NOTESApplies to output and bidirectional pins: DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, TIMEXP, HBG, REDY, DMAG1,
DMAG2, BR6-1, CPA, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT3-0, LxCLK, LxACK, BMS, TDO, EMU, ICSA.See “Output Drive Currents” for typical drive current capabilities.Applies to input pins:ACK SBTS, IRQ2-0, HBR, CS, DMAR1, DMAR2, ID2-0, RPBA, EBOOT, LBOOT, CLKIN, RESET, TCK. Note that ACK is pulled up
internally with 2 kΩ during reset in a multiprocessor system, when ID2–0 = 001 and another ADSP-2106x is not requesting bus mastership.)Applies to input pins with internal pull-ups:DR0, DR1, TRST, TMS, TDI.Applies to three-statable pins:DATA47-0, ADDR31-0, MS3-0, RD, WR, PAGE, ADRCLK, SW, ACK, FLAG3-0, REDY, HBG, DMAG1, DMAG2, BMS, BR6–1,
TFSX, RFSX, TDO, EMU. (Note that ACK is pulled up internally with 2 kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another ADSP-2106x is
not requesting bus mastership.)Applies to three-statable pins with internal pull-ups:DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1.Applies to CPA pin.Applies to ACK pin when pulled up. (Note that ACK is pulled up internally with 2kΩ during reset in a multiprocessor system, when ID2-0 = 001 and another
ADSP-21061L is not requesting bus mastership).Applies to three-statable pins with internal pull-downs:LxDAT3-0, LxCLK, LxACK.Applies to ACK pin when keeper latch enabled.Applies to all signal pins.Guaranteed but not tested.
Specifications subject to change without notice.
POWER DISSIPATION ADSP-21061L (3.3 V)These specifications apply to the internal power portion of VDD only. See the Power Dissipation section of this data sheet for calcula-
tion of external supply current and total supply current. For a complete discussion of the code used to measure power dissipation,
see the technical note “SHARC Power Dissipation Measurements.”
Specifications are based on the following operating scenarios:
To estimate power consumption for a specific application, use the following equation where % is the amount of time your program
spends in that state:
%PEAK × IDDINPEAK + %HIGH × IDDINHIGH + %LOW × IDDINLOW + %IDLE × IDDIDLE + %IDLE16 × IDDIDLE16 = power consumption
NOTESThe test program used to measure IDDINPEAK represents worst case processor operation and is not sustainable under normal application conditions. Actual internal
power measurements made using typical applications are less than specified.IDDINHIGH is a composite average based on a range of high activity code.IDDINLOW is a composite average based on a range of low activity code.Idle denotes ADSP-21061L state during execution of IDLE instruction.Idle16 denotes ADSP-21061L state during execution of IDLE16 instruction.
ADSP-21061/ADSP-21061L
TIMING SPECIFICATIONS
GENERAL NOTESThe following timing specifications are target specifications and
are based on device simulation only.
The timing specifications shown are based on a CLKIN frequency
of 40 MHz (tCK = 25 ns). The DT derating allows specifications
at other CLKIN frequencies (within the min–max range of the
tCK specification; see Clock Input below). DT is the differ-
ence between the actual CLKIN period and a CLKIN period
of 25 ns:
DT = tCK – 25 ns
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of others.
While addition or subtraction would yield meaningful results for
an individual device, the values given in this data sheet reflect
statistical variations and worst cases. Consequently, you cannot
meaningfully add parameters to derive longer times.
See Figure 26 under Test Conditions for voltage reference
levels.
Switching Characteristics specify how the processor changes its
signals. You have no control over this timing—circuitry external
to the processor must be designed for compatibility with these
signal characteristics. Switching characteristics tell you what the
processor will do in a given circumstance. You can also use switch-
ing characteristics to ensure that any timing requirement of a de-
vice connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the proces-
sor operates correctly with other devices.
(O/D) = Open Drain
(A/D) = Active Drive
ABSOLUTE MAXIMUM RATINGS (3.3 V DEVICE)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS (5 V DEVICE)*Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Output Voltage Swing . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pF
Junction Temperature Under Bias . . . . . . . . . . . . . . . . 130°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 seconds) . . . . . . . . . . . . . . . . . +280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only; functional operation of the device at these or
any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
ESD SENSITIVITYESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2106x features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
tCKL
tCKH
tCKL
tCKH
Figure 8.Clock Input
NOTESApplies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).Only required if multiple ADSP-2106xs must come out of reset synchronous to CLKIN with program counters (PC) equal (i.e., for a SIMD system). Not required
for multiple ADSP-2106xs communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself after reset.
Figure 9.Reset
ADSP-21061/ADSP-21061LFigure 10.Interrupts
Figure 11.Timer
NOTEFlag inputs meeting these setup and hold times will affect conditional instructions in the following instruction cycle.
tDRLD
tHDA
tHDRH
tDAAK
tDSAK
Switching Characteristics:
tDRHA
tRW
W = (number of wait states specified in WAIT register) × tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTESData Delay/Setup: User must meet tDAD or tDRLD or synchronous specification tSSDATI.The falling edge of MSx, SW, and BMS is referenced.Data Hold: User must meet tHDA or tHDRH or synchronous specification tHSDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold
times given capacitive and dc loads.ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High).
Figure 13.Memory Read—Bus Master
Memory Read—Bus MasterUse these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
ADSP-21061/ADSP-21061LW = (number of wait states specified in WAIT register) × tCK.
H = tCK (if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
I = tCK (if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
NOTESACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for asser-
tion of ACK (High)The falling edge of MSx, SW, and BMS is referenced.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
Figure 14.Memory Write—Bus Master
Memory Write—Bus MasterUse these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the ADSP-21061 is
the bus master accessing external memory space. These switching
characteristics also apply for bus master synchronous read/write
timing (see Synchronous Read/Write—Bus Master). If these
timing requirements are met, the synchronous read/write timing
can be ignored (and vice versa).
Synchronous Read/Write—Bus MasterUse these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-21061 (in multiprocessor memory space). These
synchronous switching characteristics are also valid during
asynchronous memory reads and writes (see Memory Read—
Bus Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-21061 must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
tSSDATI (50 MHz)
tHSDATI
tDAAK
tSACKC
tHACK
Switching Characteristics:
tDADRO
tHADRO
tDPGC
tDRDO
tDWRO
tDWRO (50 MHz)
tDRWL
tSDDATO
tDATTR
tDADCCK
tADRCK
tADRCKH
W = (number of Wait states specified in WAIT register) × tCK.
NOTESThis specification applies to the ADSP-21061KS-200 (5 V, 50 MHz) operating at tCK < 25 ns. For all other devices, use the preceding timing specification of the
same name.ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC for deassertion of ACK (Low), all three specifications must be met for assertion
of ACK (High).Data Hold: User must meet tHDA or tHDRH or synchronous specification tHDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold
times given capacitive and dc loads.See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
ADSP-21061/ADSP-21061LFigure 15.Synchronous Read/Write—Bus Master
