ADSP-2104KP-80 ,Low Cost DSP Microcomputerscharacteristics.20 MIPS with a 50 ns instruction cycle time. The ADSP-2104Land ADSP-2109L are 3.3 v ..
ADSP-2104KP-80 ,Low Cost DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 3Environmental Conditions . . . . . . . . . . . . ..
ADSP2104KP-80 ,Low Cost DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 1268-Lead PLCC . . . . . . . . ..
ADSP-2105 ,Single-Chip Microcomputers: 16-Bit, 20 MIPS, 5v, 1 Serial PortOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2105BP-55 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
ADSP-2105BP-80 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-25KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-33KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-40VC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM1-G , High Dynamic Range Gain Block
ADSP-2104KP-80-ADSP2104KP-80
Low Cost DSP Microcomputers
FUNCTIONAL BLOCK DIAGRAMREV.0
Low Cost DSP Microcomputers
SUMMARY
16-Bit Fixed-Point DSP Microprocessors with
On-Chip Memory
Enhanced Harvard Architecture for Three-Bus
Performance: Instruction Bus & Dual Data Buses
Independent Computation Units: ALU, Multiplier/
Accumulator, and Shifter
Single-Cycle Instruction Execution & Multifunction
Instructions
On-Chip Program Memory RAM or ROM
& Data Memory RAM
Integrated I/O Peripherals: Serial Ports and Timer
FEATURES
20 MIPS, 50 ns Maximum Instruction Rate
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and
Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory (e.g., EPROM )
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering, and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction
PLCC Package
GENERAL DESCRIPTIONThe ADSP-2104 and ADSP-2109 processors are single-chip
microcomputersoptimizedfordigitalsignalprocessing(DSP)
and other high speed numeric processing applications. The
ADSP-2104/ADSP-2109 processors are built upon a common
core. Each processor combines the core DSP architecture—
computation units, data address generators, and program
sequencer—with differentiating features such ason-chip
program and data memory RAM (ADSP-2109 contains 4K
words of program ROM), a programmable timer, and two
serial ports.
Fabricated in a high speed, submicron, double-layer metal
CMOS process, the ADSP-2104/ADSP-2109 operates at
20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L
and ADSP-2109L are 3.3 volt versions which operate at
13.824 MIPS with a 72.3 ns instruction cycle time. Every
instruction can execute in a single cycle. Fabrication in CMOS
results in low power dissipation.
The ADSP-2100 Family’s flexible architecture and compre-
hensive instruction set support a high degree of parallelism.
In one cycle the ADSP-2104/ADSP-2109 canperformallthefollowing operations:Generate the next program address•Fetch the next instruction•Perform one or two data moves•Update one or two data address pointers•Perform a computation•Receive and transmit data via one or two serial ports
The ADSP-2104 contains 512 words of program RAM, 256
words of data RAM, an interval timer, and two serial ports.
The ADSP-2104L is a 3.3 volt power supply version of the
ADSP-2104; it is identical to the ADSP-2104 in all other
characteristics.
The ADSP-2109 contains 4K words of program ROM and
256 words of data RAM, an interval timer, and two serial ports.
The ADSP-2109L is a 3.3 volt power supply version of the
ADSP-2109; it is identical to the ADSP-2109 in all other
characteristics.
ADSP-2104/ADSP-2109The ADSP-2109 is a memory-variant version of the ADSP-
2104 and contains factory-programmed on-chip ROM program
memory.
The ADSP-2109 eliminates the need for an external boot EPROM
in your system, and can also eliminate the need for any external
program memory by fitting the entire application program in
on-chip ROM. This device provides an excellent option for
volume applications where board space and system cost constraints
are of critical concern.
Development ToolsThe ADSP-2104/ADSP-2109 processors are supported by a
complete set of tools for system development. The ADSP-2100
Family Development Software includes C and assembly
language tools that allow programmers to write code for any
ADSP-21xx processor. The ANSI C compiler generates ADSP-
21xx assembly source code, while the runtime C library provides
ANSI-standard and custom DSP library routines. The ADSP-
21xx assembler produces object code modules which the linker
combines into an executable file. The processor simulators provide
an interactive instruction-level simulation with a reconfigurable,
windowed user interface. A PROM splitter utility generates
PROM programmer compatible files.
EZ-ICE® in-circuit emulators allow debugging of ADSP-2104
systems by providing a full range of emulation functions such as
modification of memory and register values and execution
breakpoints. EZ-LAB® demonstration boards are complete DSP
systems that execute EPROM-based programs.
The EZ-Kit Lite is a very low cost evaluation/development
platform that contains both the hardware and software needed
to evaluate the ADSP-21xx architecture.
Additional details and ordering information is available in the
ADSP-2100 Family Software & Hardware Development Tools data
sheet (ADDS-21xx-TOOLS). This data sheet can be requested
from any Analog Devices sales office or distributor.
Additional InformationThis data sheet provides a general overview of ADSP-2104/
ADSP-2109 processor functionality. For detailed design
information on the architecture and instruction set, refer to the
ADSP-2100 Family User’s Manual, available from Analog
Devices.
SPECIFICATIONS (ADSP-2104L/ADSP-2109L) . . . . . .16
Recommended Operating Conditions . . . . . . . . . . . . . . . .16
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .16
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . .17
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . .18
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . .18
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING PARAMETERS (ADSP-2104/ADSP-2109) . . . . .20
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
TIMING PARAMETERS (ADSP-2104L/ADSP-2109L) . .27
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Interrupts & Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Bus Request–Bus Grant . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
PIN CONFIGURATIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PACKAGE OUTLINE DIMENSIONS
68-Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EZ-ICE and EZ-LAB are registered trademarks of Analog Devices, Inc.
TABLE OF CONTENTSGENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . .1
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . .3
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Program Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . .6
Program Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Data Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Boot Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Low Power IDLE Instruction . . . . . . . . . . . . . . . . . . . . . . .8
ADSP-2109 Prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Ordering Procedure for ADSP-2109 ROM Processors . . . .9
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPECIFICATIONS (ADSP-2104/ADSP-2109) . . . . . . . .12
Recommended Operating Conditions . . . . . . . . . . . . . . . .12
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .12
Supply Current & Power . . . . . . . . . . . . . . . . . . . . . . . . . .13
Power Dissipation Example . . . . . . . . . . . . . . . . . . . . . . . .14
Environmental Conditions . . . . . . . . . . . . . . . . . . . . . . . . .14
Capacitive Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
ARCHITECTURE OVERVIEWFigure 1 shows a block diagram of the ADSP-2104/ADSP-2109
architecture. The processor contains three independent compu-
tational units: the ALU, the multiplier/accumulator (MAC), and
the shifter. The computational units process 16-bit data directly
and have provisions to support multiprecision computations.
The ALU performs a standard set of arithmetic and logic
operations; division primitives are also supported. The MAC
performs single-cycle multiply, multiply/add, and multiply/
subtract operations. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations. The shifter can be used to efficiently implement
numeric format control including multiword floating-point
representations.
The internal result (R) bus directly connects the computational
units so that the output of any unit may be used as the input of
any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units.
The sequencer supports conditional jumps, subroutine calls,
and returns in a single cycle. With internal loop counters and
loop stacks, the ADSP-2104/ADSP-2109 executes looped code
with zero overhead—no explicit jump instructions are required
to maintain the loop. Nested loops are also supported.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
circular buffers. The circular buffering feature is also used by
the serial ports for automatic data transfers to (and from) on-
chip memory.
Efficient data transfer is achieved with the use of five internal
buses:Program Memory Address (PMA) BusProgram Memory Data (PMD) BusData Memory Address (DMA) BusData Memory Data (DMD) BusResult (R) Bus
The two address buses (PMA, DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD, DMD) share a single external data bus.
The BMS, DMS, and PMS signals indicate which memory
space is using the external buses.
Program memory can store both instructions and data, permit-
ting the ADSP-2104/ADSP-2109 to fetch two operands in a
single cycle, one from program memory and one from data
memory. The processor can fetch an operand from on-chip
program memory and the next instruction in the same cycle.
The memory interface supports slow memories and memory-
mapped peripherals with programmable wait state generation.
External devices can gain control of the processor’s buses with
the use of the bus request/grant signals (BR, BG).
One bus grant execution mode (GO Mode) allows the ADSP-
2104/ADSP-2109 to continue running from internal memory.
A second execution mode requires the processor to halt while
buses are granted.
Figure 1. ADSP-2104/ADSP-2109 Block Diagram
R Bus
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
DMA BUS
PMA BUS
DMD BUS
PMD BUS
ADSP-2104/ADSP-2109The ADSP-2104/ADSP-2109 can respond to several different
interrupts. There can be up to three external interrupts,
configured as edge- or level-sensitive. Internal interrupts can be
generated by the timer and serial ports. There is also a master
RESET signal.
Booting circuitry provides for loading on-chip program memory
automatically from byte-wide external memory. After reset,
three wait states are automatically generated. This allows, for
example, the ADSP-2104 to use a 150 ns EPROM as external
boot memory. Multiple programs can be selected and loaded
from the EPROM with no additional hardware.
The data receive and transmit pins on SPORT1 (Serial Port 1)
can be alternatively configured as a general-purpose input flag
and output flag. You can use these pins for event signalling to
and from an external device.
A programmable interval timer can generate periodic interrupts.
A 16-bit count register (TCOUNT) is decremented every n
cycles, where n–1 is a scaling value stored in an 8-bit register
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial PortsThe ADSP-2104/ADSP-2109 processor includes two synchro-
nous serial ports (“SPORTs”) for serial communications and
multiprocessor communication.
The serial ports provide a complete synchronous serial interface
with optional companding in hardware. A wide variety of
framed or frameless data transmit and receive modes of opera-
tion are available. Each SPORT can generate an internal
programmable serial clock or accept an external serial clock.
Each serial port has a 5-pin interface consisting of the following
signals:
The serial ports offer the following capabilities:
Bidirectional—Each SPORT has a separate, double-bufferedtransmit and receive function.
Flexible Clocking—Each SPORT can use an external serialclock or generate its own clock internally.
Flexible Framing—The SPORTs have independent framingfor the transmit and receive functions; each function can run in
a frameless mode or with frame synchronization signals inter-
nally generated or externally generated; frame sync signals may
be active high or inverted, with either of two pulse widths and
timings.
Different Word Lengths—Each SPORT supports serial dataword lengths from 3 to 16 bits.
Companding in Hardware—Each SPORT provides optional
Flexible Interrupt Scheme—Receive and transmit functionscan generate a unique interrupt upon completion of a data word
transfer.
Autobuffering with Single-Cycle Overhead—Each SPORTcan automatically receive or transmit the contents of an entire
circular data buffer with only one overhead cycle per data word;
an interrupt is generated after the transfer of the entire buffer is
completed.
Multichannel Capability (SPORT0 Only)—SPORT0provides a multichannel interface to selectively receive or
transmit a 24-word or 32-word, time-division multiplexed serial
bit stream; this feature is especially useful for T1 or CEPT
interfaces, or as a network communication scheme for multiple
processors.
Alternate Configuration—SPORT1 can be alternativelyconfigured as two external interrupt inputs (IRQ0, IRQ1) and
the Flag In and Flag Out signals (FI, FO).
InterruptsThe interrupt controller lets the processor respond to interrupts
with a minimum of overhead. Up to three external interrupt
input pins, IRQ0, IRQ1, and IRQ2, are provided. IRQ2 is
always available as a dedicated pin; IRQ1 and IRQ0 may be
alternately configured as part of Serial Port 1. The ADSP-2104/
ADSP-2109 also supports internal interrupts from the timer,
and serial ports. The interrupts are internally prioritized and
individually maskable (except for RESET which is nonmaskable).
The IRQx input pins can be programmed for either level- or
edge-sensitivity. The interrupt priorities are shown in Table I.
Table I.Interrupt Vector Addresses & PriorityThe ADSP-2104/ADSP-2109 uses a vectored interrupt scheme:
when an interrupt is acknowledged, the processor shifts program
control to the interrupt vector address corresponding to the
interrupt received. Interrupts can be optionally nested so that a
higher priority interrupt can preempt the currently executing
interrupt service routine. Each interrupt vector location is four
instructions in length so that simple service routines can be
coded entirely in this space. Longer service routines require an
additional JUMP or CALL instruction.
Individual interrupt requests are logically ANDed with the bits
in the IMASK register; the highest-priority unmasked interrupt
is then selected.
The interrupt control register, ICNTL, allows the external
interrupts to be set as either edge- or level-sensitive. Depending
on bit 4 in ICNTL, interrupt service routines can either be
nested (with higher priority interrupts taking precedence) or be
processed sequentially (with only one interrupt service active at
a time).
The interrupt force and clear register, IFC, is a write-only register
that contains a force bit and a clear bit for each interrupt.
When responding to an interrupt, the ASTAT, MSTAT, and
IMASK status registers are pushed onto the status stack and
the PC counter is loaded with the appropriate vector address.
The status stack is seven levels deep to allow interrupt nesting.
The stack is automatically popped when a return from the
interrupt instruction is executed.
Pin DefinitionsTable II shows pin definitions for the ADSP-2104/ADSP-2109
processors. Any inputs not used must be tied to VDD.
SYSTEM INTERFACEFigure 3 shows a typical system for the ADSP-2104/ADSP-2109,
with two serial I/O devices, a boot EPROM, and optional external
program and data memory. A total of 14.25K words of data
memory and 14.5K words of program memory is addressable.
Programmable wait-state generation allows the processors to
easily interface to slow external memories.
The ADSP-2104/ADSP-2109 also provides either: one external
interrupt (IRQ2) and two serial ports (SPORT0, SPORT1), or
three external interrupts (IRQ2, IRQ1, IRQ0) and one serial
port (SPORT0).
Clock SignalsThe ADSP-2104/ADSP-2109’s CLKIN input may be driven by
a crystal or by a TTL-compatible external clock signal. The
CLKIN input may not be halted or changed in frequency during
operation, nor operated below the specified low frequency limit.
If an external clock is used, it should be a TTL-compatible
signal running at the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
Because the processor includes an on-chip oscillator circuit, an
external crystal may also be used. The crystal should be con-
nected across the CLKIN and XTAL pins, with two capacitors
connected as shown in Figure 2. A parallel-resonant, fundamen-
tal frequency, microprocessor-grade crystal should be used.
Table II. ADSP-2104/ADSP-2109 Pin DefinitionsGND
SPORT0
SPORT1
or Interrupts & Flags:
NOTESUnused data bus lines may be left floating.
ADSP-2104/ADSP-2109Figure 2.External Crystal Connections
A clock output signal (CLKOUT) is generated by the processor,
synchronized to the processor’s internal cycles.
ResetThe RESET signal initiates a complete reset of the processor.
The RESET signal must be asserted when the chip is powered
up to assure proper initialization. If the RESET signal is applied
during initial power-up, it must be held long enough to allow
the processor’s internal clock to stabilize. If RESET is activated
at any time after power-up and the input clock frequency does
not change, the processor’s internal clock continues and does
not require this stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is
applied to the processor and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 tCK cycles will ensure that the PLL has locked (this does
not, however, include the crystal oscillator start-up time).
During this power-up sequence the RESET signal should be
held low. On any subsequent resets, the RESET signal must
meet the minimum pulse width specification, tRSP.
To generate the RESET signal, use either an RC circuit with an
external Schmidt trigger or a commercially available reset IC.
(Do not use only an RC circuit.)
The RESET input resets all internal stack pointers to the empty
stack condition, masks all interrupts, and clears the MSTAT
register. When RESET is released, the boot loading sequence is
performed (provided there is no pending bus request and the
chip is configured for booting, with MMAP = 0). The first
instruction is then fetched from internal program memory
location 0x0000.
Program Memory InterfaceThe on-chip program memory address bus (PMA) and on-chip
program memory data bus (PMD) are multiplexed with the on-
chip data memory buses (DMA, DMD), creating a single
external data bus and a single external address bus. The external
data bus is bidirectional and is 24 bits wide to allow instruction
fetches from external program memory. Program memory may
contain code and data.
The external address bus is 14 bits wide.
The data lines are bidirectional. The program memory select
(PMS) signal indicates accesses to program memory and can be
used as a chip select signal. The write (WR) signal indicates a
write operation and is used as a write strobe. The read (RD)
signal indicates a read operation and is used as a read strobe or
output enable signal.
The processor writes data from the 16-bit registers to 24-bit
program memory using the PX register to provide the lower
eight bits. When the processor reads 16-bit data from 24-bit
program memory to a 16-bit data register, the lower eight bits
are placed in the PX register.
The program memory interface can generate 0 to 7 wait states
for external memory devices; default is to 7 wait states after
RESET.
D23-22
A13-0
D15-8
D23-0
D23-8
A13-0
A13-0
Program Memory MapsProgram memory can be mapped in two ways, depending on
the state of the MMAP pin. Figure 4 shows the ADSP-2104
program memory maps. Figure 5 shows the program memory
maps for the ADSP-2109.
0x01FF
0x0200
0x3FFF
0x0000
0x39FF
0x3A00
0x3FFF
0x0000
MMAP=0MMAP=1
No Booting
0x37FF
0x3800
0x07FF
0x0800Figure 4.ADSP-2104 Program Memory Maps
0x3FFF
0x0000
0x3FFF
0x0000
MMAP=0MMAP=1
0x37FF
0x3800
0x0FF0
0x0FFF
0x1000
0x0FF0
0x0FFF
0x1000Figure 5.ADSP-2109 Program Memory Maps
ADSP-2104When MMAP = 0, on-chip program memory RAM occupies
512 words beginning at address 0x0000. Off-chip program
memory uses the remaining 14K words beginning at address
0x0800. In this configuration–when MMAP = 0–the boot
loading sequence (described below in “Boot Memory Inter-
face”) is automatically initiated when RESET is released.
When MMAP = 1, 14K words of off-chip program memory
begin at address 0x0000 and on-chip program memory RAM is
Data Memory InterfaceThe data memory address bus (DMA) is 14 bits wide. The
bidirectional external data bus is 24 bits wide, with the upper 16
bits used for data memory data (DMD) transfers.
The data memory select (DMS) signal indicates access to data
memory and can be used as a chip select signal. The write (WR)
signal indicates a write operation and can be used as a write
strobe. The read (RD) signal indicates a read operation and can
be used as a read strobe or output enable signal.
The ADSP-2104/ADSP-2109 processors support memory-
mapped I/O, with the peripherals memory-mapped into the data
memory address space and accessed by the processor in the
same manner as data memory.
Data Memory Map
ADSP-2104On-chip data memory RAM resides in the 256 words beginning
at address 0x3800, also shown in Figure 6. Data memory
locations from 0x3900 to the end of data memory at 0x3FFF
are reserved. Control and status registers for the system, timer,
wait-state configuration, and serial port operations are located in
this region of memory.
Figure 6.Data Memory Map
The remaining 14K of data memory is located off-chip. This
external data memory is divided into five zones, each associated
with its own wait-state generator. This allows slower peripherals
to be memory-mapped into data memory for which wait states
are specified. By mapping peripherals into different zones, you
can accommodate peripherals with different wait-state require-
ments. All zones default to seven wait states after RESET.
ADSP-2104/ADSP-2109
Boot Memory InterfaceBoot memory is an external 16K by 8 space, divided into eight
separate 2K by 8 pages. The 8-bit bytes are automatically
packed into 24-bit instruction words by the processor, for
loading into on-chip program memory.
Three bits in the processors’ System Control Register select
which page is loaded by the boot memory interface. Another bit
in the System Control Register allows the forcing of a boot
loading sequence under software control. Boot loading from
Page 0 after RESET is initiated automatically if MMAP = 0.
The boot memory interface can generate zero to seven wait
states; it defaults to three wait states after RESET. This allows
the ADSP-2104 to boot from a single low cost EPROM such as
a 27C256. Program memory is booted one byte at a time and
converted to 24-bit program memory words.
The BMS and RD signals are used to select and to strobe the
boot memory interface. Only 8-bit data is read over the data
bus, on pins D8-D15. To accommodate up to eight pages of
boot memory, the two MSBs of the data bus are used in the
boot memory interface as the two MSBs of the boot memory
address: D23, D22, and A13 supply the boot page number.
The ADSP-2100 Family Assembler and Linker allow the
creation of programs and data structures requiring multiple boot
pages during execution.
The BR signal is recognized during the booting sequence. The
bus is granted after loading the current byte is completed. BR
during booting may be used to implement booting under control
of a host processor.
Bus InterfaceThe ADSP-2104/ADSP-2109 can relinquish control of their
data and address buses to an external device. When the external
device requires control of the buses, it asserts the bus request
signal (BR). If the processor is not performing an external
memory access, it responds to the active BR input in the next
cycle by:Three-stating the data and address buses and the PMS,
DMS, BMS, RD, WR output drivers,Asserting the bus grant (BG) signal,•and halting program execution.
If the Go mode is set, however, the ADSP-2104/ADSP-2109
will not halt program execution until it encounters an instruc-
tion that requires an external memory access.
If the processor is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces or assert the BG signal until the cycle
after the access completes (up to eight cycles later depending on
the number of wait states). The instruction does not need to be
completed when the bus is granted; the processor will grant the
bus in between two memory accesses if an instruction requires
more than one external memory access.
When the BR signal is released, the processor releases the BG
signal, re-enables the output drivers and continues program
execution from the point where it stopped.
The bus request feature operates at all times, including when
the processor is booting and when RESET is active. If this
feature is not used, the BR input should be tied high (to VDD).
Low Power IDLE InstructionThe IDLE instruction places the processor in low power state in
which it waits for an interrupt. When an interrupt occurs, it is
serviced and execution continues with instruction following
IDLE. Typically this next instruction will be a JUMP back to
the IDLE instruction. This implements a low-power standby
loop.
The IDLE n instruction is a special version of IDLE that slows
the processor’s internal clock signal to further reduce power
consumption. The reduced clock frequency, a programmable
fraction of the normal clock rate, is specified by a selectable
divisor, n, given in the IDLE instruction. The syntax of the
instruction is:
IDLE n;
where n = 16, 32, 64, or 128.
The instruction leaves the chip in an idle state, operating at the
slower rate. While it is in this state, the processor’s other
internal clock signals, such as SCLK, CLKOUT, and the timer
clock, are reduced by the same ratio. Upon receipt of an
enabled interrupt, the processor will stay in the IDLE state for
up to a maximum of n CLKIN cycles, where n is the divisor
specified in the instruction, before resuming normal operation.
When the IDLE n instruction is used, it slows the processor’s
internal clock and thus its response time to incoming interrupts–
the 1-cycle response time of the standard IDLE state is in-
creased by n, the clock divisor. When an enabled interrupt is
received, the ADSP-21xx will remain in the IDLE state for up
to a maximum of n CLKIN cycles (where n = 16, 32, 64, or
128) before resuming normal operation.
When the IDLE n instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the IDLE state (a maximum of n
CLKIN cycles).
ADSP-2109 PrototypingYou can prototype your ADSP-2109 system with the ADSP-
2104 RAM-based processor. When code is fully developed and
debugged, it can be submitted to Analog Devices for conversion
into a ADSP-2109 ROM product.
The ADSP-2101 EZ-ICE emulator can be used for develop-
ment of ADSP-2109 systems. For the 3.3 V ADSP-2109, a
voltage converter interface board provides 3.3 V emulation.
Additional overlay memory is used for emulation of ADSP-2109
systems. It should be noted that due to the use of off-chip
overlay memory to emulate the ADSP-2109, a performance loss
may be experienced when both executing instructions and
fetching program memory data from the off-chip overlay
memory in the same cycle. This can be overcome by locating
program memory data in on-chip memory.
Ordering Procedure for ADSP-2109 ROM ProcessorTo place an order for a custom ROM-coded ADSP-2109, you
must:
1. Complete the following forms contained in the ADSP ROM
Ordering Package, available from your Analog Devices sales
representative:
ADSP-2109 ROM Specification Form
ROM Release Agreement
ROM NRE Agreement & Minimum Quantity Order (MQO)
Acceptance Agreement for Pre-Production ROM Products
2. Return the forms to Analog Devices along with two copies of
the Memory Image File (.EXE file) of your ROM code. The
files must be supplied on two 3.5" or 5.25" floppy disks for
the IBM PC (DOS 2.01 or higher).
3. Place a purchase order with Analog Devices for nonrecurring
engineering changes (NRE) associated with ROM product
development.
After this information is received, it is entered into Analog
Devices’ ROM Manager System which assigns a custom ROM
model number to the product. This model number will be
branded on all prototype and production units manufactured to
these specifications.
To minimize the risk of code being altered during this process,
Analog Devices verifies that the .EXE files on both floppy disks
are identical, and recalculates the checksums for the .EXE file
entered into the ROM Manager System. The checksum data, in
the form of a ROM Memory Map, a hard copy of the .EXE file,
and a ROM Data Verification form are returned to you for
inspection.
A signed ROM Verification Form and a purchase order for
production units are required prior to any product being
manufactured. Prototype units may be applied toward the
minimum order quantity.
Upon completion of prototype manufacture, Analog Devices
will ship prototype units and a delivery schedule update for
production units. An invoice against your purchase order for the
NRE charges is issued at this time.
There is a charge for each ROM mask generated and a mini-
mum order quantity. Consult your sales representative for
details. A separate order must be placed for parts of a specific
package type, temperature range, and speed grade.
ADSP-2104/ADSP-2109
Instruction SetThe ADSP-2104/ADSP-2109 assembly language uses an algebraic
syntax for ease of coding and readability. The sources and
destinations of computations and data movements are written
explicitly in each assembly statement, eliminating cryptic
assembler mnemonics.
Every instruction assembles into a single 24-bit word and
executes in a single cycle. The instructions encompass a wide
variety of instruction types along with a high degree of
operational parallelism. There are five basic categories of
instructions: data move instructions, computational instruc-
tions, multifunction instructions, program flow control instruc-
tions and miscellaneous instructions. Multifunction instructions
perform one or two data moves and a computation.
The instruction set is summarized below. The ADSP-2100
Family Users Manual contains a complete reference to the
instruction set.
ALU Instructions[IF cond]AR|AF=xop + yop [+ C] ;Add/Add with Carryxop – yop [+ C– 1] ;Subtract X – Y/Subtract X – Y with Borrowyop – xop [+ C– 1] ;Subtract Y – X/Subtract Y – X with Borrowxop AND yop ;ANDxop OR yop ;ORxop XOR yop ;XORPASS xop ;Pass, Clear– xop ;NegateNOT xop ;NOTABS xop ;Absolute Valueyop + 1 ;Incrementyop – 1 ;DecrementDIVS yop, xop ;DivideDIVQ xop ;
MAC Instructions[IF cond]MR|MF=xop * yop ;MultiplyMR + xop * yop ;Multiply/AccumulateMR – xop * yop ;Multiply/SubtractMR ;Transfer MR
=0 ;Clear
IF MV SAT MR ;Conditional MR Saturation
Shifter Instructions[IF cond]SR = [SR OR] ASHIFT xop ;Arithmetic Shift
[IF cond]SR = [SR OR] LSHIFT xop ;Logical Shift
SR = [SR OR] ASHIFT xop BY
;Arithmetic Shift Immediate
SR = [SR OR] LSHIFT xop BY ;Logical Shift Immediate
[IF cond]SE = EXP xop ;Derive Exponent
[IF cond]SB = EXPADJ xop ;Block Exponent Adjust
[IF cond]SR = [SR OR] NORM xop ;Normalize
Data Move Instructions
reg = reg ;Register-to-Register Move
reg = ;Load Register Immediate
reg = DM () ;Data Memory Read (Direct Address)
dreg = DM (Ix , My) ;Data Memory Read (Indirect Address)
dreg = PM (Ix , My) ;Program Memory Read (Indirect Address)
DM () = reg ;Data Memory Write (Direct Address)
DM (Ix , My) = dreg ;Data Memory Write (Indirect Address)
PM (Ix , My) = dreg ;Program Memory Write (Indirect Address)
Multifunction Instructions
|| , dreg = dreg ;Computation with Register-to-Register Move
|| , dreg = DM (Ix , My) ;Computation with Memory Read
|| , dreg = PM (Ix , My) ;Computation with Memory Read
DM (Ix , My) = dreg , || ;Computation with Memory Write
PM (Ix , My) = dreg , || ;Computation with Memory Write
dreg = DM (Ix , My) , dreg = PM (Ix , My) ;Data & Program Memory Read
Program Flow Instructions
DO [UNTIL term] ;Do Until Loop
[IF cond] JUMP (Ix) ;Jump
[IF cond] JUMP ;
[IF cond] CALL (Ix) ;Call Subroutine
[IF cond] CALL ;
IF [NOT ] FLAG_INJUMP ;Jump/Call on Flag In Pin
IF [NOT ] FLAG_INCALL ;
[IF cond] SET|RESET|TOGGLE FLAG_OUT [, ...] ;Modify Flag Out Pin
[IF cond] RTS ;Return from Subroutine
[IF cond] RTI ;Return from Interrupt Service Routine
IDLE [(n)] ;Idle
Miscellaneous Instructions
NOP ;No Operation
MODIFY (Ix , My);Modify Address Register
[PUSH STS] [, POP CNTR] [, POP PC] [, POP LOOP] ;Stack Control
ENA|DISSEC_REG [, ...] ;Mode Control
BIT_REV
AV_LATCH
AR_SAT
M_MODE
TIMER
G_MODE
Notation ConventionsIndex registers for indirect addressingModify registers for indirect addressing
Immediate data value
Immediate address value
Exponent (shift value) in shift immediate instructions (8-bit signed number)
Any ALU instruction (except divide)
Any multiply-accumulate instruction
Any shift instruction (except shift immediate)
condCondition code for conditional instruction
termTermination code for DO UNTIL loop
dregData register (of ALU, MAC, or Shifter)
regAny register (including dregs)A semicolon terminates the instructionCommas separate multiple operations of a single instruction
[ ]Optional part of instruction
[, ...]Optional, multiple operations of an instruction
option1 | option2List of options; choose one.
Assembly Code Example
The following example is a code fragment that performs the filter tap update for an adaptive filter based on a least-mean-squared
algorithm. Notice that the computations in the instructions are written like algebraic equations.
MF=MX0*MY1(RND), MX0=DM(I2,M1);{MF=error*beta}
MR=MX0*MF(RND), AY0=PM(I6,M5);
DO adapt UNTIL CE;
AR=MR1+AY0, MX0=DM(I2,M1), AY0=PM(I6,M7);
adapt:PM(I6,M6)=AR, MR=MX0*MF(RND);
MODIFY(I2,M3);{Point to oldest data}
MODIFY(I6,M7);{Point to start of data}
RECOMMENDED OPERATING CONDITIONS
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
VIH
VIL
VOL
IIL
NOTESInput-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.Three-state pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.Input-only pins: RESET, IRQ2, BR, MMAP, DR1, DR0.0 V on BR, CLKIN Active (to force three-state condition).Although specified for TTL outputs, all ADSP-2104/ADSP-2109 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.Guaranteed but not tested.Applies to PGA, PLCC, PQFP package types.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ADSP-2104/ADSP-2109–SPECIFICATIONS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADSP-2104/ADSP-2109 processor features proprietary ESD protection circuitry to dissipate
high energy electrostatic discharges (Human Body Model), permanent damage may occur to devices
subjected to such discharges. Therefore, proper ESD precautions are recommended to avoid
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . .–55ºC to +125°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +125°C
Lead Temperature (10 sec) PGA . . . . . . . . . . . . . . . . .+300°C
Lead Temperature (5 sec) PLCC, PQFP, TQFP . . . .+280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
SPECIFICATIONS (ADSP-2104/ADSP-2109)
SUPPLY CURRENT & POWER
NOTESCurrent reflects device operating with no output loads.VIN = 0.4 V and 2.4 V.Idle refers to ADSP-2104/ADSP-2109 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
For typical supply current (internal power dissipation) figures, see Figure 7.
Figure 7.ADSP-2104/ADSP-2109 Power (Typical) vs. Frequency
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-2104/ADSP-2109 OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3 MAXIMUM POWER DISSIPATION AT VDD = 5.5V DURING EXECUTION OF IDLE n INSTRUCTION.
POWER – mW
FREQUENCY – MHz
IDD IDLE n MODES3
POWER – mW
FREQUENCY – MHz
IDD DYNAMIC1
POWER – mW
FREQUENCY – MHz
IDD IDLE1, 2
ADSP-2104/ADSP-2109
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 ×f
C = load capacitance,f= output switching frequency.
Example:
In an ADSP-2104 application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:External data memory is accessed every cycle with 50% of the
address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.The application operates at VDD = 5.0 V and tCK = 50 ns.
Total Power Dissipation = PINT + (C × VDD2 ×f)
PINT = internal power dissipation (from Figure 7).
(C × VDD2 × f) is calculated for each output:
70.0 mW
Total power dissipation for this example = PINT + 70.0 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
SPECIFICATIONS(ADSP-2104/ADSP-2109)CAPACITIVE LOADING
Figures 8 and 9 show capacitive loading characteristics.
Figure 8.Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
Figure 9.Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
CL – pF1001255075150
VALID OUTPUT DELAY OR HOLD – ns
1750
TEST CONDITIONS
Figure 10 shows voltage reference levels for ac measurements.
3.0V
1.5V
0.0V
2.0V
1.5V
0.8V
INPUT
OUTPUT
Figure 10.VoltageReferenceLevels for AC Measurements
(Except Output Enable/Disable)
Output Disable Time
Output pins are considered to be disabled when they have
stopped driving and started a transition from the measured
output high or low voltage to a high impedance state. The
output disable time (tDIS) is the difference of tMEASURED and
tDECAY, as shown in Figure 11. The time tMEASURED is the
interval from when a reference signal reaches a high or low
voltage level to when the output voltages have changed by 0.5 V
from the measured output high or low voltage.
The decay time, tDECAY, is dependent on the capacitative load,
CL, and the current load, iL, on the output pin. It can be
approximated by the following equation:
tDECAY=CL×0.5VL
from which
tDIS = tMEASURED – tDECAY
is calculated. If multiple pins (such as the data bus) are dis-
abled, the measurement value is that of the last pin to stop
driving.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (tENA) is the interval from
when a reference signal reaches a high or low voltage level to
when the output has reached a specified high or low trip point,
as shown in Figure 11. If multiple pins (such as the data bus)
are enabled, the measurement value is that of the first pin to
start driving.
SPECIFICATIONS (ADSP-2104/ADSP-2109)
tENA
REFERENCE
SIGNAL
VOH (MEASURED)
OUTPUT STOPS
DRIVING
OUTPUT STARTS
DRIVING
VOL (MEASURED)
VOH (MEASURED)
VOL (MEASURED)
Figure 11. Output Enable/Disable
OUTPUT
PIN
+1.5V
IOH
IOL
RECOMMENDED OPERATING CONDITIONS
See “Environmental Conditions” for information on thermal specifications.
ELECTRICAL CHARACTERISTICS
VIL
VOH
VOL
IIH
IIL
NOTESInput-only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR1, DR0.Output pins: BG, PMS, DMS, BMS, RD, WR, A0–A13, CLKOUT, DT1, DT0.Bidirectional pins: D0–D23, SCLK1, RFS1, TFS1, SCLK0, RFS0, TFS0.Three-stateable pins: A0–A13, D0–D23, PMS, DMS, BMS, RD, WR, DT1, SCLK1, RSF1, TFS1, DT0, SCLK0, RFS0, TFS0.0 V on BR, CLKIN Active (to force three-state condition).All outputs are CMOS and will drive to VDD and GND with no dc loads.Guaranteed but not tested.Applies to PLCC package type.Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
ADSP-2104L/ADSP-2109L–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +4.5 V
Input Voltage . . . . . . . . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Output Voltage Swing . . . . . . . . . . . . . .–0.3 V to VDD + 0.3 V
Operating Temperature Range (Ambient) . . . .–40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (5 sec) PLCC . . . . . . . . . . . . . . . .+280°C
*Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these
or any other conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
SUPPLY CURRENT & POWER (ADSP-2104L/ADSP-2109L)
NOTESCurrent reflects device operating with no output loads.VIN = 0.4 V and 2.4 V.Idle refers to ADSP-2104L/ADSP-2109L state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.
For typical supply current (internal power dissipation) figures, see Figure 13.
Figure 13. ADSP-2104L/ADSP-2109L Power (Typical) vs. Frequency
1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS.
2 IDLE REFERS TO ADSP-2104L/ADSP-2109L OPERATION DURING EXECUTION OF IDLE INSTRUCTION.
DEASSERTED PINS ARE DRIVEN TO EITHER VDD OR GND.
3 MAXIMUM POWER DISSIPATION AT VDD = 3.6V DURING EXECUTION OF IDLE n INSTRUCTION.
POWER – mW
IDD IDLE1
FREQUENCY – MHz
POWER – mW
IDLE DYNAMIC 1,2
FREQUENCY – MHz
POWER – mW
FREQUENCY – MHz
IDD IDLE n MODES3
ADSP-2104/ADSP-2109
SPECIFICATIONS (ADSP-2104L/ADSP-2109L)
CAPACITIVE LOADING
Figures 14 and 15 show capacitive loading characteristics.
POWER DISSIPATION EXAMPLE
To determine total power dissipation in a specific application,
the following equation should be applied for each output:
C × VDD2 ×f
C = load capacitance,f= output switching frequency.
Example:
In an ADSP-2104L application where external data memory is
used and no other outputs are active, power dissipation is
calculated as follows:
Assumptions:External data memory is accessed every cycle with 50% of the
address pins switching.External data memory writes occur every other cycle with
50% of the data pins switching.Each address and data pin has a 10 pF total load at the pin.The application operates at VDD = 3.3 V and tCK = 100 ns.
Total Power Dissipation = PINT + (C × VDD2 ×f)
PINT = internal power dissipation (from Figure 13).
(C × VDD2 × f) is calculated for each output:
Data, WR
15.25 mW
Total power dissipation for this example = PINT + 15.25 mW.
ENVIRONMENTAL CONDITIONS
Ambient Temperature Rating:
TAMB = TCASE – (PD × θCA)
TCASE = Case Temperature in °C
PD = Power Dissipation in W
θCA = Thermal Resistance (Case-to-Ambient)
θJA = Thermal Resistance (Junction-to-Ambient)
θJC = Thermal Resistance (Junction-to-Case)
Figure 14. Typical Output Rise Time vs. Load Capacitance, CL
(at Maximum Ambient Operating Temperature)
Figure 15. Typical Output Valid Delay or Hold vs. Load
Capacitance, CL (at Maximum Ambient Operating Temperature)
