ADSP-2100AJG ,12.5 MIPS DSP Microprocessorspecifications differ as shown in those sections of the data sheet.
Both processors integrate co ..
ADSP-2101BP-100 ,ADSP-2100 Family DSP MicrocomputersOVERVIEW . . . . . . . . . . . . . . . . . . . . 4Supply Current & Power . . . . . . . . . . . . . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 2180-Lead PQFP, 80-Lead TQFP . ..
ADSP-2101BP-66 ,ADSP-2100 Family DSP MicrocomputersFEATURES(ADSP-2111)25 MIPS, 40 ns Maximum Instruction Rate ADSP-2100 CORE Separate On-Chip Buses fo ..
ADSP-2101BS-100 ,ADSP-2100 Family DSP Microcomputersfeatures plus 80K bytes of on-chip RAMand, on the ADSP-2111, a host interface port.configured as 16 ..
ADSP-2101BS-66 ,ADSP-2100 Family DSP MicrocomputersADSP-2100 FamilyaDSP MicrocomputersADSP-21xxFUNCTIONAL BLOCK DIAGRAMSUMMARY16-Bit Fixed-Point DSP M ..
AM186ED-40KC , ADVANCED MICROCONTROLLER from the Am186ED/EDLV family made from original AMD wafers
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-20KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-25KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-33KC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
AM188EM-40VC , EMBEDDED STORAGE PRODUCT used in everyday office applications 16-Bit Microcontroller
ADSP-2100AJG
12.5 MIPS DSP Microprocessor
ANALOG
DEVICES
FEATURES
Pin- and Code-Compatible DSP Microprocessors
ADSP-2100, 6.144MHz and 8.192MH2
ADSP-2100A, 10.24MHz and 12.5MHz
Separate Program and Data Buses, Extended Off-Chip
Single-Cycle Direct Access to 16K x 16 of Data Memory
Single-Cycle Direct Access to 32K x 24 of Program
Memory
Dual Purpose Program Memory for Both Instruction
and Data Storage
Three Independent Computational Units: ALU,
Multiplier/Accumulator and Barrel Shifter
Two Independent Data Address Generators
Powerful Program Sequencer
Internal Instruction Cache
Provisions for Multiprecision Computation and
Saturation Logic
Single-Cycle Instruction Execution
Multifunction Instructions
Four External Interrupts
80ns Cycle Time (ADSP-2100A)
790mW Maximum Power Dissipation (ADSP-2100A,
J and K Grades)
100-Pin Grid Array, 100-Lead POFP (JEDEC Style)
APPLICATIONS
Optimized for DSP Algorithms Including
Digital Filtering
Fast Fourier Transforms
Applications Include
Image Processing
Radar, Sonar
Speech Processing
Telecommunications
GENERAL DESCRIPTION
The ADSP-2100 and ADSP-2100A are pin- and code-compatible
single-chip microprocessors optimized for digital signal processing
(DSP) and other high-speed numeric processing applications.
The ADSP-2100 and ADSP-2100A are both fabricated in a low-
power double-layer metal CMOS process. Together, they offer a
span of performance from 6MHz to 12,5MHz. All descriptions
of the ADSP-2100 in the text of this data sheet refer to both the
ADSP-2100A and the ADSP-2100 versions since they have
identical architectures and instruction sets. Timing and electrical
specifications differ as shown in those sections of the data sheet.
Both processors integrate computational units, data address
generators and a program sequencer in a single device. The
ADSP-2100 architecture makes efficient use of external memories
for program and data storage, freeing silicon area for increased
Information furnished by Analog Devices is believed to be accurate
and reliable. However, no responsibility is assumed by Analog Devices
for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implica-
tion or otherwise under any patent or patent rights of Analog Devices.
12.5 MIPS DSP Microprocessor
processor performance. The resulting processor combines the
functions and performance of a bit-slice/building block system
with the ease of design and development support of a general
purpose microprocessor.
The ADSP-2100A (K grade) operates at 12.5MH2. Every in-
struction executes in a single 80ns cycle. The ADSP-2100A (J
and K grades) dissipates less than 790mW while the ADSP-2100
dissipates less than 475mW.
The ADSP-2100's flexible architecture and comprehensive in-
struction set support a high degree of operational parallelism.
Because all instructions execute in a single cycle, MHz = MIPS.
In one cycle the ADSP-2100 can:
. generate the next program address
fetch the next instruction
q perform one or two data moves
0 update one or two data address pointers
O perform a computational operation.
DEVELOPMENT SYSTEM
The ADSP-2100 and ADSP-2100A are supported by a complete
set of tools for software and hardware system development. The
Cross-Software System provides a System Builder for defining
the architecture of simulated systems under development, an
Assembler, a Linker and a interactive Simulator. An ANSI
(draft) Standard C Compiler supports program development in
this widely used programming language, producing ADSP-ZIOO
Assembly code which may be assembled, linked and simulated
with the other development system tools. A PROM Splitter
generates PROM burner compatible files. An In-Circuit Emulator
is available for hardware debugging.
An Evaluation Board is available for quick assessment of actual
processor performance in a prepackaged hardware environment.
One Technology Way; P. O. Box 9106; Norwood, MA 02062-9106 U.S.A.
Tel: 617/329-4700 Twx: 710/3M-6577
Telex: 924491 Cables: ANALOG NORWOODMASS
ADDITIONAL INFORMATION
For additional information on the architecture and instruction
set of the processor, refer to the ADSP-2100 User's Manual.
For more information about programming and the Development
System, refer to the ADSP-2100 Cross-Software Manual and the
ADSP-2100 Emulator Manual. For examples of applications
routines, refer to the ADSP-2 100 Applications Handbook, Volume
1, 2 or 3. Manuals are available only from your local Analog
Devices sales office. There is also a quarterly newsletter,
DSPatch'rM, supporting Analog Devices' digital signal processing
customers.
ARCHITECTURE OVERVIEW
Figure l is an overall block diagram of the ADSP-2100. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the Shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primitives
are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations. The Shifter
performs logical and arithmetic shifts, normalization, denormali-
zation and derive exponent operations. The Shifter can be used
to efficiently implement any degree of numeric format control,
up to and including full floating point representations. The
computational units are arranged side-by-side instead of serially
for flexible operation sequencing. The internal result (R) bus
directly connects the computational units so that the output of
any unit may be the input of any unit on the next cycle.
A powerful program sequencer and two dedicated data address
generators ensure efficient use of these computational units. The
program sequencer generates the next instruction address. To
minimize overhead cycles, the sequencer supports conditional
jumps, subroutine calls and returns in a single cycle. With
internal loop counters and loop stacks, the ADSP-2100 executes
looped code with zero overhead; no explicit jump instructions
are required to maintain the loop.
The data address generators (DAGs) handle address pointer
updates. Each DAG keeps track of up to four address pointers.
Whenever the pointer is used to access external data (indirect
addressing), it is modified by a prespecified value. A length
value may be associated with each pointer to implement automatic
modulo addressing for circular buffers. With two independent
DAGs, the processor can generate two addresses simultaneously
for dual operand fetches.
Efficient data transfer is achieved with the use of five internal
buses.
q Program Memory Address (PMA) bus
q Program Memory Data (PMD) bus
. Data Memory Address (DMA) bus
q Data Memory Data (DMD) bus
0 Result (R) bus
DSPatch is a trademark of Analog Devices, Inc.
Figure 1. ADSP-2100 Block Diagram
MEMORY
fl INSTRUCTION
() () REGISTER
DATA DATA JVl
ADDRESS ADDRESS
cs PMA
PMA BUS 14/
r I *1
N 7 N 7 DMA BUS 14/ N 7
Pub BUS 24,
EXCHANGE
1s, 4 7 DMD BUS
() g I 1E
INPUT REGS INPUT REGS INPUT REGS
ALU MAC SHIFTER
OUTPUT REGS OUTPUT macs OUTPUT REGS
R L n BUS , L 15, S L
The program memory (PMD, PMA) buses and data memory
(DMA, DMD) buses extend off-chip to provide direct connections
to external memories. The DMD bus is the primary bus for
routing data internally and to/from external data memory. The
14-bit DMA bus provides direct addressing of 16K x 16 of external
memory. Although the primary function of the program memory
is for storing instructions, it can also store data. In this case, the
PMD bus provides a path for routing data to/from program
memory, permitting dual operand fetches. The 14-bit PMA bus
provides direct addressing of 16K M 24 of external memory,
expandable to 32K X 24 by using the program memory data
access (PMDA) signal as the 15th address line.
When a data fetch from program memory is required, an extra
memory cycle is automatically appended to enable the next
instruction fetch. To avoid this extra cycle, the ADSP-2100 has
an internal instruction cache (l6 instructions deep) which serves
as an alternate source for the next instruction. The cache monitor
circuit transparently determines when the cache contents are
valid. When the next instruction is in the cache, no extra cycle
is necessary.
Pin Description
The data memory interface supports slower memories and memory-
mapped peripherals with wait states. The data memory ac-
knowledge (DMACK) signal provides the necessary handshake.
External devices can gain control of program or data buses
independently with bus request) grant signals (W, and E).
The ADSP-2100 can respond to four external interrupts, which
are internally prioritized, maskable and independently pro-
grammable as either edge- or level-sensitive. Additional external
controls arepovided by the RESET, HALT and TRAP signals.
With both BR and RESET recognized, the ADSP-2100 idles,
consuming the least possible current.
The ADSP-2100 instruction set provides flexible data moves
and multifunction (data moves with a computation) instructions.
Every instruction can be executed in a single processor cycle.
The ADSP-2100 assembly language uses an algebraic syntax for
ease of coding and readability. A comprehensive set of development
tools supports program development.
A pin description and detailed discussion of each section of the
ADSP-2100 follows.
This section summarizes the pin description of the processor by interface. In this data sheet, when groups of pins are identified
with subscripts, as in PMD2ro, the highest numbered pin (PMD23) is the MSB.
Master input clock operating at four times the processor instruction rate. Nominally 50% duty
cycle. The phases of CLKIN define the eight internal processor states making up one instruction
Pin Name Type Function
Clocks:
CLKIN Input
cycle.
CLKOUT Output
the internal processor states.
Interrupt Request Lines:
IRQ3, 0 Input
and individually maskable.
Control Interface:
Output clock operating at the processor instruction rate with a 50% duty cycle. Synchronized to
Interrupt Request lines that may be either edge triggered or level sensitive. Interrupts are prioritized
Master Reset must be asserted long enough to assure proper reset. When RESET is released,
Used to halt the processor. All control signals become inactive and the address and data buses are
Used to indicate the execution of a TRAP instruction. Remains asserted until HALT is asserted
Bus Request used by an external device to request control of the program and data memory interface.
Upon receiving W the processor halts execution at the completion of the current cycle and relinquishes
the program and data memory interface by tristating PMA, PMD, PMS, PMWR, PMRD, PMDA,
DMA, DMD, ITM-S, DMRD and DMWR. The processor regains control when W is released.
RESET Input
execution begins at program memory location 0004.
HALT Input
driven for observation.
TRAP Output
by an external device.
W Input
BE Output
Program Memory Interface:
PMA13_0 Output
PMD23_0 Bidirectional
PMS Output
B_us Grant. Acknowledgesibus request (W), indicating that the external device may take control.
BG is held asserted until BR is released.
Program Memory Address Bus; tristated when B-tf is asserted.
Program Memory Data Bus; tristated when E is asserted.
Program Memory Select signals a program memory access on the PM interface. Usable as a chip
select signal for external memories. Remains asserted on successive program memory accesses. HI
only when the processor is halted or after execution of a TRAP instruction. Tristated when BG is
asserted.
Program Memory Interface:
PMRD Output
PMWR Output
PMDA Output
Data Memory Interface:
DMA13_0 Output
DMIhr 0 Bidirectional
DMS Output
DMRD Output
DMWR Output
DMACK Input
Supply Rails:
Program Memory Read indicates a read operation on the PM interface. Also usable as a read
strobe or output enable signal. Tristated when BG is asserted.
Program Memory Write establishes the direction of data transfer on the PM interface. Also usable
as a write strobe. Tristated when BG is asserted.
Program Memory Data Access used to distinguish instruction and data fetches from PM. Asserted
high when dataiss opposed to instruction, are accessed. Also usable as a fifteenth PM address bit.
Tristated when BG is asserted.
Data Memory Address Bus; tristated when E is asserted.
Data Memory Data Bus; tristated when E is asserted.
Data Memory Select signals a Data Memory Access on the Data Memory interface. Usable as a
chip select signal for external memories. Remains asserted on successive data memory accesses.
HI only when the processor is halted or after execution of a TRAP instruction. Tristated when
E is asserted.
Data Memory Read indicates a read operation on the Data Memory interface. Also usable as a
read strobe or output enable signal. Tristated when BG is asserted.
Data Memory Write indicates a write operation on the Data Memory interface. Also usable as a
write strobe. Tristated when BG is asserted.
Data Memory Acknowledge signal used for asynchronous transfers across the DM interface, Indicates
that data memory or memory-mapped peripherals are ready for data transfer. If DMACK is not
asserted when checked by the processor, wait states are automatically generated until DMACK is
asserted.
VDD Supply Power supply rail nominally + SVDC. There are four Vm, pins.
GND Ground Power supply return. There are nine GND pins.
pm, BUS 24/ and logic functions: add, subtract, negate, increment, decrernent,
I Ali; (UPPER) absolute value, AND, OR, Exclusive OR and NOT. Two divide
DMD BUS 16/ p' primitives are also provided to facilitate division. The ALU
I takes two 16-bit inputs, X and Y, and generates one 16-bit
output, R. It accepts the carry (AC) bit in the arithmetic status
register (ASTAT) as the carry-in (CI) bit. The carry-in feature
AX AY enables multiprecision computations. Six arithmetic status bits
"Ef'fjgnj '"ri'T,y" are generated: AZ (zero), AN (negative), AV (overflow), AC
L YT---- (carry), AS (sign) and AQ (quotient). These status bits are
- Ali; latched in ASTAT.
MUX l The X input port can be fed by either the AX register file or
any result registers on the R-bus (AR, MRO, MRI, MR2, SRO,
or SR1). The AX register file contains two registers, AXO and
X AXI. The AX registers can be loaded from the DMD bus. The
A2 M- . . .
AN _ Y Input port can be fed by either the AY register file or the
25 t ALU feedback (AF) register. The AY register file contains two
fd t- registers, AYO and AYl. The AY registers can be loaded from
R " either the DMD bus or the PMD bus.
A The register file outputs are dual ported so that one register can
16 / drive the ALU input while either one simultaneously drives the
DMD bus. The ALU output can be latched in either the AR
register or the AF register.
The AR register has a saturation capability; it can automatically
REGAISTER output plus or minus the maximum value if an overflow or
underflow occurs. The saturation mode is enabled by a bit in
the mode status register (MSTAT). The AR register can drive
both the R-bus and the DMD bus and can be loaded from the
' R . BUS DMD bus.
Figure 2. ALU Block Diagram The ALU contains a duplicate bank of registers shown in Figure
. . . 2 as a "shadow" behind the primary registers. The secondary
Irithmttie/Logic Unit . . . . . set contains all the registers described above (AXO, AXl, AYO,
Figure 2 shows a block diagram of the Arithmetic/Logic Unit AYl, AF, AR). Only one set is accessible at a time. The two
(ALU). sets of registers allow fast context switching for interrupt servicing.
The ALU provides a standard set of general purpose arithmetic The active set is determined by a bit in MSTAT.
