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ADS6425IRGCR-ADS6425IRGCT
Quad 12-bit 125MSPS ADC with serialized LVDS output
1FEATURES APPLICATIONS
DESCRIPTION
ADS6425
www.ti.com......................................................................................................................................................... SLWS197B–MARCH 2007–REVISED JUNE 2009
QUAD CHANNEL, 12-BIT, 125-MSPS ADC WITH SERIAL LVDS INTERFACE Base-StationIF Receivers•
Maximum Sample Rate: 125 MSPS Diversity Receivers•
12-Bit Resolution with No Missing Codes Medical Imaging•
1.65-W Total Power •
Test Equipment•
Simultaneous Sample and Hold 70.3 dBFS SNRat Fin=50 MHz 83 dBc SFDRat Fin= 50 MHz,0 dB Gain The ADS6425 is a high performance 12-bit,•
79 dBc SFDRat Fin= 170 MHz, 3.5 dB Gain 125-MSPS quad channel ADC. Serial LVDS data•
3.5 dB Coarse Gain and upto6 dB outputs reduce the numberof interface lines, resulting
Programmable Fine Gain for SFDR/SNR ina compact 64-pin QFN package(9 mm×9 mm)
that allows for high system integration density. The
Trade-Offdevice includesa 3.5 dB coarse gain option that can•
Serialized LVDS Outputs with Programmable be usedto improve SFDR performance with little
Internal Termination Option degradationin SNR.In additionto the coarse gain,•
Supports Sine, LVCMOS, LVPECL, LVDS Clock fine gain options also exist, programmablein 1dB
Inputs and Amplitude Downto 400 mVpp steps upto 6dB.
Differential The output interfaceis 2-wire, where each ADC's•
Internal Reference with External Reference datais serialized and output over two LVDS pairs.
Support This makesit possibleto halve the serial data rate
(comparedtoa 1-wire interface) and restrictitto less•
No External Decoupling Required forthan 1Gbps easing receiver design. The ADS6425
References also includes the traditional 1-wire interface that can•
3.3-V Analog and Digital Supply be usedat lower sampling frequencies.•
64 QFN Package(9 mm×9 mm) An internal phase locked loop (PLL) multiplies the•
Pin Compatible 14-Bit Family (ADS644X- incoming ADC sampling clockto derive thebit clock.
SLAS532) Thebit clockis usedto serialize the 12-bit data from
each channel.In additionto the serial data streams,
the frame and bit clocks are also transmitted as
LVDS outputs. The LVDS output buffers have
features such as programmable LVDS currents,
current doubling modes, and internal termination
options. These can be usedto widen eye-openings
and improve signal integrity, easing capture by the
receiver.
The ADC channel outputs can be transmitted either MSBor LSB first and 2s complementor straight
binary.
The ADS6425 has internal references, but can also
support an external reference mode. The deviceis
specified over the industrial temperature range
(–40°Cto 85°C).
