ADS62P15IRGCR ,Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs 64-VQFN -40 to 85Block Diagram(1)PACKAGE/ORDERING INFORMATIONSPECIFIED TRANSPORT(2)PACKAGE- PACKAGE LEAD/BALL PACKAG ..
ADS62P15IRGCT ,Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs 64-VQFN -40 to 85FEATURES Reference also• 64-QFN Package (9mm× 9mm)• Maximum Sample Rate: 125 MSPS• Pin Compatible 1 ..
ADS62P22IRGCR ,Dual 12-bit 65MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85FEATURES• High Definition Video• Medical Imaging• Maximum Sample Rate: 125 MSPS• Radar Systems• 12- ..
ADS62P22IRGCT ,Dual 12-bit 65MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
ADS62P23IRGCR ,Dual 12-bit 80MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85FEATURES• High Definition Video• Medical Imaging• Maximum Sample Rate: 125 MSPS• Radar Systems• 12- ..
ADS62P23IRGCT ,Dual 12-bit 80MSPS ADC with selectable DDR LVDS or CMOS outputs 64-VQFN -40 to 85This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated cir ..
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ADS62P15IRGCR-ADS62P15IRGCT
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
ADS62P15
www.ti.com SLAS572C–OCTOBER 2007–REVISED FEBRUARY 2012
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
Checkfor Samples: ADS62P15
1FEATURES Reference also 64-QFN Package (9mm×
9mm)•
Maximum Sample Rate: 125 MSPS Pin Compatible 14-bit and 12-bit Family•
11-Bit Resolution With No Missing Codes
(ADS62P4X/ADS62P2X)•
84 dBc SFDRat Fin= 50 MHz 67.1 dBFS SNRat Fin=50 MHz APPLICATIONS•
92 dB Crosstalk •
Wireless Communications Infrastructure•
Parallel CMOS and DDR LVDS Output Options •
Software Defined Radio•
3.5 dB Coarse Gain and Programmable Fine •
Power Amplifier LinearizationGain upto6 dB for SNR/SFDR Trade-Off •
802.16d/e•
Digital Processing Block With: Medical Imaging–
Offset Correction Radar Systems–
Fine Gain Correction,in Stepsof 0.05 dB •
Test and Measurement Instrumentation–
Decimation by 2/4/8 Built-in and Custom Programmable 24-Tap Table1. ADS62PXX Dual Channel Family
Low/High /Band Pass Filters•
Supports Sine, LVPECL, LVDS&
LVCMOSClocks&
Amplitude Downto 400 mVPP•
Clock Duty Cycle Stabilizer•
Internal Reference; Supports External
DESCRIPTIONADS62P15isa dual channel 11-bit A/D converter with maximum sample ratesupto 125 MSPS.It combines high
performance and low power consumptionina compact64 QFN package. Usingan internal sample and hold and
low jitter clock buffer, the ADC supports high SNR and high SFDRat high input frequencies.It has coarse and
fine gain options that canbe usedto improve SFDR performanceat lower full-scale input ranges.
ADS62P15 includesa digital processing block that consistsof several useful and commonly used digital offset correction, fine gain correction (in stepsof 0.05 dB), decimation by 2,4,8 and filters. By default, the digital processing blockis bypassed, andits functions exist– parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes pins and associated have been eliminated.an externalis specified over the industrial
