ADS62C15IRGCR ,Dual Channel 11-Bits, 125 MSPS ADC With SNRBoost 64-VQFN -40 to 85FEATURES• Maximum Sample Rate: 125 MSPS• Supports Sine, LVPECL, LVDS and LVCMOSClocks and Amplitude ..
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ADS62C15IRGCR-ADS62C15IRGCT
Dual Channel 11-Bits, 125 MSPS ADC With SNRBoost
ADS62C15
www.ti.com SLAS577E –JANUARY 2008–REVISED FEBRUARY 2012
Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs
Checkfor Samples: ADS62C15
1FEATURES Maximum Sample Rate: 125 MSPS •
Supports Sine, LVPECL, LVDS and LVCMOS
Clocks and Amplitude Downto 400 mVPP•
11-Bit Resolution With No Missing Codes Clock Duty Cycle Stabilizer•
82 dBc SFDRat Fin= 117 MHz Internal Reference; Also Supports External•
67 dBFS SNRat Fin= 117 MHz
Reference•
77.5 dBFS SNRat Fin= 117 MHz, 20MHz •
64-QFN Package (9mm×
9mm)bandwidth using SNRBoost technology 92 dB Crosstalk APPLICATIONS•
Parallel CMOS and DDR LVDS Output Options •
Wireless Communications Infrastructure•
3.5 dB Coarse Gain and Programmable Fine •
Software Defined RadioGain upto6 dB for SNR/SFDR Trade-Off Power Amplifier Linearization•
Digital Processing Block With: 802.16d/e–
Offset Correction Medical Imaging–
Fine Gain Correction,in Stepsof 0.05 dB Radar Systems–
Decimation by 2/4/8 Test and Measurement Instrumentation–
Built-in and Custom Programmable 24-Tap
Low/High /Band Pass Filters
DESCRIPTIONADS62C15isa dual channel 11-bit A/D converter with maximum sample rates upto 125 MSPS.It combines
high performance and low power consumptionina compact64 QFN package. Usingan internal sample and hold
and low jitter clock buffer, the ADC supports high SNR and high SFDRat high input frequencies.It has coarse
and fine gain options that canbe usedto improve SFDR performanceat lower full-scale input ranges.
ADS62C15 uses proprietary SNRBoost technology that can be usedto overcome SNR limitation dueto
quantization noise (for bandwidths less than Nyquist, Fs/2).It includesa digital processing block that consistsof
several useful and commonly used digital functions suchas ADC offset correction, fine gain correction (in steps 0.05 dB), decimationby 2,4,8 and in-built and custom programmable filters. By default, the digital processing
blockis bypassed, andits functions are disabled. exist– parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes traditional reference pins and associated decoupling capacitors have been eliminated. driven an external reference. The deviceis specified over the industrial temperature
