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ADS6145IRHBT
Low Power 14-bit 125MSPS ADC with selectable parallel CMOS or LVDS outputs
1FEATURES
DESCRIPTION
APPLICATIONS
ADS6145, ADS6144
ADS6143, ADS6142SLWS198B–JULY 2007–REVISED MARCH 2008
www.ti.com
14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS Radar Systems Maximum Sample Rate: 125 MSPS 14-Bit Resolution with No Missing Codes at high input frequencies.
Inputs, and Clock Amplitude Downto 400
mVPP The ADS614X feature coarse and fine gain optionsto
improve SFDR performanceat lower full-scale analog•
Clock Duty Cycle Stabilizerinput ranges.•
Internal Reference with Support for External
Reference The digital data outputs are either parallel CMOSor
DDR (Double Data Rate) LVDS. Several features•
No External Decoupling Required for existto ease data capture such as — controls for
References output clock position and output buffer drive strength,•
Programmable Output Clock Position and LVDS current, and internal termination
Drive Strengthto Ease Data Capture programmability.
3.3-V Analog and 1.8-Vto 3.3-V Digital Supply The output interface type, gain, and other functions•
32-QFN Package(5 mm×
5 mm) are programmed usinga 3-wire serial interface.
Alternatively, some functions are configured using•
Pin Compatible 12-Bit Family (ADS612X)dedicated parallel pinsso the device powersupto the
desired state.
The ADS614X include internal references while•
Wireless Communications Infrastructureeliminating traditional reference pins and associated•
Software Defined Radio external decoupling. External reference modeis also•
Power Amplifier Linearization supported.•
802.16d/eThe ADS614X are specified over the industrial•
Test and Measurement Instrumentation temperature range (–40°Cto 85°C).•
High Definition Video Medical Imaging
ADS614X Performance Summary
ADS6145 ADS6144 ADS6143 ADS6142Fin=10 MHz(0dB gain) 90 91 93 95
SFDR, dBc Fin= 170 MHz (3.5dB gain) 78 82 83 84
Fin=10 MHz(0dB gain) 73.7 74.1 74.5 74.6
SINAD, dBFS Fin= 170 MHz (3.5dB gain) 68.6 70.5 70.6 71.5
Power, mW 417 374 318 285