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ADS58C48IPFP-ADS58C48IPFPR
Quad 11-Bit 200MSPS ADC with SNRBoost
ADS58C48
www.ti.com SLAS689 –MAY 2010
Quad ChannelIF Receiver with SNRBoost3G
Checkfor Samples: ADS58C48
1FEATURES DESCRIPTION Maximum Sample Rate: 200 MSPS The ADS58C48 is a quad channel 11-bit A/D
converter with sampling rateupto 200 MSPS.It uses
• High Dynamic Performanceinnovative design techniquesto achieve high dynamic
– SFDR82 dBcat 140 MHz performance, while consuming extremely low power
– 72.3 dBFS SNRin60 MHz BW Using at 1.8V supply. This makes it well-suited for
SNRBoost3G
technology multi-carrier, wide band-width communications
applications.
• SNRBoost3G
Highlights Supports Wide Bandwidth upto60 MHz The ADS58C48 uses third-generation SNRBoost3G
technology to overcome SNR limitation due to
– Programmable Bandwidths–60 MHz,40 quantization noise (for bandwidths< Nyquist, Fs/2).
MHz,30 MHz,20 MHz Enhancementsin the SNRBoost3G technology allow
– Flat Noise Floor within the Band support for SNR improvements over wide bandwidths
– Independent SNRBoost3G
Coefficients for (upto 60 MHz).In addition, separate SNRBoost3G
Every Channel coefficients canbe programmed for each channel.
Output Interface The device has digital gain function that can be used improve SFDR performance at lower full-scale
– Double Data Rate (DDR) LVDS withinput ranges.It includesa dc offset correction loop
Programmable Swing and Strengththat canbe usedto cancel the ADC offset.
– Standard Swing: 350 mVThe digital outputsofall channels are outputas DDR
– Low Swing: 200 mV LVDS (Double Data Rate) together with an LVDS
– Default Strength: 100-Ω Termination clock output. The low data rateof this interface (400
– 2x Strength: 50-Ω Termination Mbpsat 200 MSPS sample rate) makesit possibleto
use low-cost FPGA-based receivers. The strengthof
– 1.8V Parallel CMOS Interface Alsothe LVDS output buffers can be increasedto support
Supported 50-Ω differential termination. This allows the output
• Ultra-Low Power with Single 1.8-V Supply clock signalto be connectedto two separate receiver
– 0.9-W Total Power chips with an effective 50-Ω termination (suchas the
two clock portsof the GC5330).
– 1.32-W Total Power (200 MSPS) with
SNRBoost3G
on all4 Channels The same digital output pins can also be configured
(200 MSPS) with asa parallel 1.8-V CMOS interface.
2 It includes internal references while the traditional
up for SNR/SFDR reference pins and associated decoupling capacitors have been eliminated. The deviceis specified over range (–40°Cto 85°C).
Amplitude
