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ADS58C28IRGCR-ADS58C28IRGCT
Dual 11-Bit 200MSPS ADC with SNRBoost
ADS58C28
www.ti.com SBAS509B –JUNE 2010–REVISED OCTOBER 2010
Dual ChannelIF Receiver with SNRBoost3G
Checkfor Samples: ADS58C28
1FEATURES DESCRIPTION
23• Maximum Sample Rate: 200MSPS The ADS58C28 is a dual-channel, 11-bit
analog-to-digital converter (ADC) with sampling rates
• High Dynamic Performance:to 200MSPS. The device uses innovative design
– 83dBc SFDRat 140MHz techniques to achieve high dynamic performance,
– 72.5dBFS SNR with 60MHz BW Using while consuming extremely low powerat 1.8V supply.
SNRBoost3G Technology This architecture makesit well-suitedfor multi-carrier,
wide bandwidth communications applications.
• SNRBoost3G Highlights: Supports Wide Bandwidth (upto 60MHz) The ADS58C28 uses third-generation SNRBoost3G
technologyto overcome SNR limitation asa resultof
– Programmable Bandwidths:quantization noise (for bandwidths less than Nyquist,
20MHz, 30MHz, and 40MHz fS/2). Enhancementsin the SNRBoost3G technology
– Flat Noise Floor within the Band allow support for SNR improvements over wide
– Independent SNRBoost3G Coefficients for bandwidths (up to 60MHz). In addition, separate
Both Channels SNRBoost3G coefficients can alsobe programmed for
each channel.
• Output Interface:The device hasa digital gain function that can be
– Double Data Rate (DDR) LVDS withused to improve SFDR performance at lower
Programmable Swing and Strength:full-scale input ranges.It includesa dc offset
– Standard Swing: 350mV correction loop that can be usedto cancel the ADC
– Low Swing: 200mV offset. The digital outputsof all channels are output double data rate (DDR) low-voltage differential
– Default Strength: 100Ω terminationsignaling (LVDS) together withan LVDS clock output.
– 2x Strength: 50Ω termination The low data rate of this interface (400MBPSat
– Compatible with GC6016 200MSPS sample rate) makesit possible to use
1.8V Parallel CMOS Interface Also low-cost field-programmable gate array
(FPGA)-based receivers. The strengthof the LVDS
Supportedoutput buffers can be increased to support 50Ω
• Ultralow Power with Single 1.8V Supply: differential termination. This increase allows the
– 470mW Total Power output clock signalto be connectedto two separate
710mW Total Power (200MSPS) with receiver chips withan effective 50Ω termination (such the two clock portsof the GC5330). The same
Both Channelsdigital output pins can alsobe configuredasa parallel
up for 1.8V CMOS interface.
The device includes internal references while the pins and associated decoupling
Amplitude eliminated. The ADS58C28is specified over
(–40°Cto +85°C).
