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ADS58B18IRGZR-ADS58B18IRGZT
11 bit 200MSPS Buffered ADC with SNRBoost
ADS58B18
ADS58B19
www.ti.com SBAS487D– NOVEMBER 2009–REVISED JANUARY 2011
11-Bit, 200MSPS/9-Bit, 250MSPS,
Ultralow-Power ADCs with Analog Buffer
Checkfor Samples: ADS58B18, ADS58B19
1FEATURES DESCRIPTION
23• ADS58B18: 11-Bit, 200MSPS The ADS58B18/B19 are members of the ultralow
power ADS4xxx analog-to-digital converter (ADC)•
ADS58B19: 9-Bit, 250MSPSfamily that features integrated analog buffers and•
Integrated High-Impedance Analog Input SNRBoost technology. The ADS58B18 and
Buffer ADS58B19 are 11-bit and 9-bit ADCs with sampling•
Ultralow Power: rates upto 200MSPS and 250MSPS, respectively.
Innovative design techniques are usedto achieve–
Analog Power: 258mWat 200MSPShigh dynamic performance while consuming–
I/O Power: 69mW (DDR LVDS, low LVDS extremely low power. The analog input pins have
swing) buffers with constant performance and input•
High Dynamic Performance: impedance acrossa wide frequency range. This
architecture makes these parts well-suited for–
ADS58B18: 66dBFS SNR and 81dBc SFDRmulti-carrier, wide bandwidth communications
at 150MHz applications suchas PA linearization.–
ADS58B19: 55.7dBFS SNR and 76dBcThe ADS58B18 uses TI-proprietary SNRBoost
SFDRat 150MHztechnology that can be used to overcome SNR•
Enhanced SNR Using TI-Proprietary SNRBoost limitation as a result of quantization noise for
Technology (ADS58B18 Only) bandwidths less than Nyquist (fS/2).– –77.7dBFS
SNRin 20MHz Bandwidth Both devices have gain options that can be usedto•
Dynamic Power Scaling with Sample Rate improve SFDR performanceat lower full-scale input•
Output Interface: ranges, especially at very high input frequencies.
They also includeadc offset correction loop that can–
Double Data Rate (DDR) LVDS with usedto cancel the ADC offset.At lower sampling
Programmable Swing and Strength rates, the ADC automatically operatesat scaled-down–
Standard Swing: 350mV power withno lossin performance.–
Low Swing: 200mV These devices support both double data rate (DDR)–
Default Strength: 100Ω Termination low-voltage differential signaling (LVDS) and parallel The low data rateof 500Mbps) makes gate They have a usedto further strengthof theto support
