ADS41B29IRGZR ,12 bit 250MSPS Buffered Low Power ADC 48-VQFN -40 to 85Featuresand offset correction. The gain option can be used to1• ADS41B49: 14-Bit, 250 MSPSimprove S ..
ADS41B29IRGZT ,12 bit 250MSPS Buffered Low Power ADC 48-VQFN -40 to 85Electrical Characteristics: ADS41B29, ADS41B49. 1010.1 Power-Supply Sequence... 506.7 Digital Chara ..
ADS41B49IRGZR ,14 bit 250MSPS Buffered Low Power ADC 48-VQFN -40 to 85Featuresand offset correction. The gain option can be used to1• ADS41B49: 14-Bit, 250 MSPSimprove S ..
ADS41B49IRGZT ,14 bit 250MSPS Buffered Low Power ADC 48-VQFN -40 to 85Electrical Characteristics: ADS41B29, ADS41B49. 1010.1 Power-Supply Sequence... 506.7 Digital Chara ..
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ADS41B29IRGZR-ADS41B29IRGZT
12 bit 250MSPS Buffered Low Power ADC
14-Bit
ADC
OVR_SDOUT
D10_D11_M
D10_D11_P
D8_D9_M
D8_D9_P
D6_D7_M
D6_D7_P
D4_D5_M
D4_D5_P
D2_D3_M
D2_D3_P
D0_D1_M
D0_D1_P
CLKOUTM
CLKOUTP
CLKM
CLKP
CLOCKGEN
INM
VCM
INP
Sampling
Circuit
Common
Digital Functions
DDR
Serializer
Reference
Control
Interface
DFS
SEN
SCLK
RESET
ADS41B49AVDD AGND DRVDD DRGND
DDR LVDS
Interface
D12_D13_M
D12_D13_P
Analog Buffers
AVDD_BUF
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ADS41B29, ADS41B49SBAS486F –NOVEMBER 2009–REVISED FEBRUARY 2016
ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers Features ADS41B49: 14-Bit, 250 MSPS
ADS41B29: 12-Bit, 250 MSPS Integrated High-Impedance
Analog Input Buffer: Input Capacitance:2pF 200-MHz Input Resistance:3 kΩ Maximum Sample Rate: 250 MSPS Ultralow Power: 1.8-V Analog Power: 180 mW 3.3-V Buffer Power:96 mW I/O Power: 135 mW (DDR LVDS) High Dynamic Performance: SNR:69 dBFSat 170 MHz SFDR: 82.5 dBcat 170 MHz Output Interface: Double Data Rate (DDR) LVDS with
Programmable Swing and Strength: Standard Swing: 350 mV Low Swing: 200 mV Default Strength: 100-Ω Termination 2x Strength: 50-Ω Termination 1.8-V Parallel CMOS Interface Also Supported Programmable Gain for SNR, SFDR Trade-Off DC Offset Correction Supports Low Input Clock Amplitude Package: VQFN-48(7 mm×7 mm)
Applications Power Amplifier Linearization Software Defined Radio Wireless Communications Infrastructureof the ultralow-power converter (ADC) family, buffers. extremely have buffers, with and range. The
The ADS41Bx9 have features such as digital gain
and offset correction. The gain option canbe usedto
improve SFDR performanceat lower full-scale input
ranges, especially at high input frequencies. The
integrated dc offset correction loop can be usedto
estimate and cancel the ADC offset. At lower
sampling rates, the ADC automatically operatesat
scaled-down power withno lossin performance.
The devices support both double data rate (DDR)
low-voltage differential signaling (LVDS) and parallel
CMOS digital output interfaces. The low data rateof
the DDR LVDS interface (maximum 500 MBPS)
makes using low-cost field-programmable gate array
(FPGA)-based receivers possible. The devices have low-swing LVDS mode that can be usedto further
reduce the power consumption. The strengthof the
LVDS output buffers can alsobe increasedto support
50-Ω differential termination.
Device Information(1)(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
ADS41B49 Block Diagram
