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ADP3650
Dual Bootstrapped, 12V MOSFET Driver with Output Disable
ANALOG
DEVICES
Dual, Bootstrapped, 12 ll MOSFET
Driver with Output Disable
ADP365U
FEATURES
AII-in-one synchronous buck driver
Bootstrapped high-side drive
One PWM signal generates both drives
Anti-crossconduction protection circuitry
o-Dtor disabling the driver outputs
APPLICATIONS
Telecom and datacom networking
Industrial and medical systems
Point of load conversion: memory, DSP, FPGA, ASIC
GENERAL DESCRIPTION
The ADP3650 is a dual, high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, the two switches in a
nonisolated synchronous buck power converter. Each driver is
capable of driving a 3000 pF load with a 45 ns propagation delay
and a 25 ns transition time. One of the drivers can be boot-
strapped and is designed to handle the high voltage slew rate
associated with floating high-side gate drivers. The ADP3650
includes overlapping drive protection to prevent shoot-through
current in the external MOSFET;
The w, pin shuts offboth the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3650 is specified over the temperature range of -40oC
to +85''C and is available in 8-1ead SOIC_N and 8-lead LFCSP_VD
packages.
FUNCTIONAL BLOCK DIAGRAM
ADP3650
C0 NTROL
Rev. A
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msponsibilityisassumedbyAnalog Devkesfbritsustsnorfbranyinhingememsofpatentsorather
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license is granted by implication or otherwise under any patent or patent rights of Analog Davies.
Trademarks and registered trademarks arethe prrapertyaf their respective owners.
Figure 1.
INDUCTOR
07 826-001
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781 .329.4700
Fax: 781.461.3113 ©2008-201 0 Analog Devices, Inc. All rights reserved.
ADP3650
TABLE OF CONTENTS
Features m............................................................................................. 1 Low-Side Driver I........................................................................... 9
Applications _...................................................................................... 1 High-Side Driver _.......................................................................... 9
General Description ......................................................................... 1 Overlap Protection Circuit F.......................................................... 9
Functional Block Diagram P............................................................. 1 Applications Information .............................................................. 10
Revision History F.............................................................................. 2 Supply Capacitor Selection _...................................................... 10
Specifications w.................................................................................... 3 Bootstrap Circuit _....................................................................... 10
Timing Characteristics F............................................................... 4 MOSFET Selection P.................................................................... 10
Absolute Maximum Ratings V........................................................... 5 High-Side (Control) MOSFETs w............................................... 10
Thermal Resistance ...................................................................... 5 Low-Side (Synchronous) MOSFETs ........................................ 11
ESD Caution .................................................................................. 5 PCB Layout Considerations ...................................................... 11
Pin Configurations and Function Descriptions ........................... 6 Outline Dimensions w...................................................................... 12
Typical Performance Characteristics F............................................ 7 Ordering Guide _......................................................................... 12
Theory of Operation _....................................................................... 9
REVISION HISTORY
7/10-Rev. 0 to Rev. A
Changes to General Description Section ... ...
Changes to Table 1 w........................................................................... 3
Changes to Operating Ambient Temperature Range Parameter,
Table 2 F............................................................................................... 5
Changes to Figure 8 and Figure 9 _.................................................. 7
Changes to Ordering Guide .......................................................... 12
10/ 08-Revision 0: Initial Version
Rev. A l Page 2 of 12
ADP365U
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = -40''C to +85°C, unless otherwise noted.1
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DIGITAL INPUTS (IME)
InputVoltage High 2.0 V
Input Voltage Low 0.8 V
Input Current -1 +1 pA
Hysteresis 40 250 350 mV
HlGH-SIDE DRIVER
Output Resistance, Sourcing Current BST - SW = 12 V;TA = 25''C 3.3 fl
BST - SW = 12 V; TA = -40''C to +85°C 2.5 3.9 fl
Output Resistance, Sinking Current BST - SW = 12 V;TA = 25°C 1.8 ft
BST - SW = 12 V; TA = -40t'C to +85°C 1.4 2.6 ft
Output Resistance, Unbiased BST - SW = 0 V 10 k0
Transition Times trDRVH BST - SW = 12 V, CLOAD = 3 nF, see Figure 3 25 40 ns
thRVH BST - SW = 12 V, CLOAD = 3 nF, see Figure 3 20 30 ns
Propagation Delay Times tpthRVH BST - SW = 12 V, CLOAD = 3 nF, 32 45 70 ns
25°C 3 TA s: 85°C, see Figure 3
tpdlDRVH BST - SW = 12 V, CLOAD = 3 nF, see Figure 3 25 35 ns
th'oT) See Figure 2 20 35 ns
tpdho-D See Figure 2 40 55 ns
SW Pull-Down Resistance SW to PGND 10 k0
LOW-SIDE DRIVER
Output Resistance, Sourcing Current TA = 25°C 3.3 fl
TA = -40oC to +85''C 2.4 3.9 fl
Output Resistance, Sinking Current TA = 25°C 1.8 ft
TA = -4YC to +85''C 1.4 2.6 ft
Output Resistance, Unbiased VCC = PGND 10 k0
Transition Times trDRVL CLOAD = 3 nF, see Figure 3 20 35 ns
thRVL CLOAD = 3 nF, see Figure 3 16 30 ns
Propagation Delay Times tpthRVL CLOAD = 3 nF, see Figure 3 12 35 ns
tpdlDRVL CLOAD = 3 nF, see Figure 3 30 45 ns
tpdlcf) See Figure 2 20 35 ns
tpdho-D See Figure 2 110 190 ns
Timeout Delay SW = 5 V 110 190 ns
SW = PGND 95 150 ns
SUPPLY
Supply Voltage Range Vcc 4.15 13.2 V
Supply Current lsvs BST = 12 V, IN = O V 2 5 mA
UVLO Voltage Vcc rising 1.5 3.0 V
Hysteresis 350 mV
l All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Rev.A l Page 3 of 12
ADP3650
TIMING CHARACTERISTICS
Timing is referenced to the 90% and 10% points, unless otherwise noted.
tpdlDRVL thRVL
tpmo-D
tpoo-D
tpthRVH
Figure 3. Timing Diagram
Rev. A l Page 4 of 12
Figure 2. Output Disable Timing Diagram
tpdlDRVH
‘pthRVL
trDRVL
ADP365U
ABSOLUTE MAXIMUM RATINGS
All voltages are referenced to PGND, unless otherwise noted.
Table 2.
Parameter Rating
VCC -0.3Vto +15V
DC -0.3VtoVCC+ 15V
<200 ns -0.3 V to +35 V
BSTto SW -0.3Vto +15V
DC -5 V to +1 5 V
<200 ns -10Vto +25V
DC sw- 0.3Vto BST+ 0.3V
<200 ns sw- 2Vto BST+ 0.3V
DC -0.3 V to VCC + 0.3 V
<200 ns -2Vto VCC+0.3V
IN, E -0.3 v to +6.5 v
Operating AmbientTemperature Range -40oC to +85''C
Junction Temperature Range 0°C to 150°C
Storage Temperature Range -65oC to +150°C
Lead Temperature
Soldering (1 0 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
' is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type th, Unit
8-Lead SOIC_N (R-8)
2-Layer Board 123 °C/W
4-Layer Board 90 °C/W
8-Lead LFCSP_VD‘ (CP-8-2)
4-Layer Board 50 °C/W
l For LFCSP_VD, GM is measured perJEDEC STD with exposed pad soldered to PCB.
ESD CAUTION
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary protection circuitry, damage
dt E A may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to
avoid performance degradation or loss of functionality.
Rev.A l Page 5 of 12