ADP3502ASU-REEL Fast Delivery |IC PHOENIX CO.,LIMITED

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ADP3502ASU-REEL
CDMA Power Management System
REV.0
CDMA Power Management System
FEATURES
11 LDOs Optimized for Specific CDMA Subsystems
4 Backup LDOs for Standby Mode Operation
Ultra Low Standby Supply Current
High Accuracy Battery Charger (0.7%)
3 Li-Ion Battery Charge Modes
5 mA Precharge
Low Current Charge
Full Current Charge
Integrated RTC
Ambient Temperature: –30�C to +85�C
64-Lead 7 mm � 7 mm � 1 mm TQFP Package
APPLICATIONS
CDMA/CDMA2000/PCS Handsets
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The ADP3502 is a multifunction chip optimized for CDMA-1x
cell phone power management. It offers a total power solution
for the handset baseband and RF section, including LDOs to
power 11 subsystems. Also integrated are a real-time clock
(RTC), serial bus interface, and charging control for Li-Ion/
Li-Polymer batteries. Sophisticated controls are available for
power-up during battery charging, keypad interface, GPIO/INT
function, and RTC function.
The ADP3502 is optimized for CDMA handsets powered by
single-cell Li-Ion batteries. Its high level of integration sig-
nificantly reduces the design effort, number of discrete
components, and solution size/cost. The main-sub LDO
structure reduces the standby current consumption, and as a
result, greatly extends the standby time of the phone. System
operation has been proven to be fully compatible with
MSM51xx-based designs.
The ADP3502 comes in a 64-lead 7 mm × 7 mm × 1 mm
TQFP package and is specified over a wide temperature range of
–30°C to +85°C.
ADP3502–SPECIFICATIONS
(TA = –30�C to +85�C, CVBAT = 1 �F MLCC, VBAT = 3.6 V, unless otherwise noted. See Table II for COUT.)
LDO SPECIFICATIONS
MAIN FUNCTIONS
(TA = 25�C, CVBAT = 1 �F MLCC, VBAT = VOUT + 1 V, NRCAP = 0.1 �F. See Table II for COUT.)
BASEBAND VDD SUB-LDO (LDO1b)
ADP3502
BASEBAND AVDD SUB-LDO (LDO2b)
COIN CELL SUB-LDO (LDO3b)
VIBRATOR LDO (LDO5)
ADP3502
LDO SPECIFICATIONS (continued)
ADP3502
BATTERY VOLTAGE DIVIDER: MVBAT
(TA = –30�C to +85�C, CVBAT = 10 �F MLCC, CADAPTER = 1 �F MLCC, unless
otherwise noted.)
BATTERY CHARGER
(TA = –30�C to +85�C, CVBAT = 10 �F MLCC, CADAPTER = 1 �F MLCC, 4.0 V � ADAPTER � 12 V, unless
otherwise noted.)
OPERATING BATTERY
ADP3502
NOTES
1Guaranteed but not tested.
2DDLO hysteresis is dependent on DDLO threshold value. If DDLO threshold is at maximum, DDLO hysteresis is at maximum at the same time.
3This includes the total reverse current from battery to BVS, BASE, ISENSE, and ADAPTER pins with no adapter present. No signal path between ADAPTER pin
and ADPSUPPLY pin.
Specifications subject to change without notice.
BATTERY CHARGER (continued)
LOGIC
DC SPECIFICATIONS(TA = 25�C, CVBAT = 1 �F MLCC, VBAT = 3.6 V, unless otherwise noted.)
ADP3502
AC SPECIFICATIONS(All specifications include temperature, unless otherwise noted.)
tCSS
tCKH
tCKL
tCSH
tCSR
tDH
tRD
SERIAL INTERFACE
LOGIC (continued)
ADP3502
ABSOLUTE MAXIMUM RATINGS*
Voltage on ADAPTER, ADPSUPPLY Pin
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, 15 V
Voltage on VBAT Pin to GND . . . . . . . . . . . . –0.3 V, +6.5 V
Voltage on Pins 6–13, 21–28
to GND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VLDO1 + 0.3 V
Voltage on Pins 1, 62–64 . . . . . . . . . . . –0.3 V, VBAT + 0.3 V
Voltage on Pins 20, 32 . . . . . . . . . . . . . –0.3 V, VRTCV + 0.3 V
Voltage on Pin 60 . . . . . . . . . . . . . . –0.3 V, VADAPTER + 0.3 V
Voltage on Pins 2–5, 14, 30, 31, 33 . . . . . . . . . –0.3 V, +6.5 V
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range . . . . . . . . . . . –30°C to +85°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3502 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125°C
�JA Thermal Impedance (TQFP-64)
(2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . .87.4°C/W
�JA Thermal Impedance (TQFP-64)
(4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . . . . 56.2°C/W
Lead Temperature Range
(Soldering, 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified all
other voltages are referenced to GND.
ORDERING GUIDE
Model
ADP3502ASU
PIN CONFIGURATION
OSC IN
GND
OSC OUT
GPIO0GPIO1GPIO2GPIO3
CLKIN
RESETIN–
32K OUT
RESET+
RESET
OUT–
TEST
OPT2–OPT1–PO
WER
ONKEY–
ISENSEADPSUPPL
APTER
MVB
GND
NRCAPBVSLDO10 (RF OPTION)VB
LDO9 (RF Rx2)A
GND
LDO8 (RF Tx)
OPT3
KEYPADCOL0
KEYPADCOL1
KEYPADCOL2
KEYPADCOL3
KEYPADROW0
KEYPADROW1
KEYPADROW2
KEYPADROW3
KEYPADROW4
KEYPADROW5
TCXOON
SLEEP–
BLIGHT
DGND
INT–
VBAT
LDO7 (REF Rx1)
LDO6 (BASEBAND CORE)
VBAT
LDO5 (VIBRATOR)
LDO4 (AUDIO)
VBAT
LDO2 (BASEBAND AVDD)
REFO
AGND
LDO3 (RTC/COIN-CELL)
VBAT
LDO1 (BASEBAND VDD)
LDO11 (OPTION)
VBAT
RSTDELAY–
PIN FUNCTION DESCRIPTION
Pin
No.
ADP3502
PIN FUNCTION DESCRIPTION (continued)
PIN FUNCTION DESCRIPTION (continued)
ADP3502
Figure 1.Overall Block Diagram
TPC 1.LDO1 Load Regulation
TPC 4.LDO8 Load Regulation
TPC 7.LDO6 Line Regulation
TPC 2.LDO4 Load Regulation
TPC 5.LDO1 Line Regulation
TPC 8.LDO8 Line Regulation
TPC 3.LDO6 Load Regulation
TPC 6.LDO4 Line Regulation
TPC 9.LDO1 Dropout Voltage
ADP3502
TPC 10.LDO4 Dropout Voltage
TPC 13.Charger Load Regulation
TPC 16.LDO4 Load Transient
TPC 11.LDO6 Dropout Voltage
TPC 14.Charger Line Regulation
TPC 17.LDO6 Line Transient
TPC 12.LDO8 Dropout Voltage
TPC 15.LDO4 Line Transient
TPC 18.LDO6 Load Transient
TPC 19.LDO8 Line Transient
TPC 22.LDO1 PSRR
TPC 25.IGND vs. Temperature
TPC 20.LDO8 Load Transient
TPC 23.LDO4 PSRR
TPC 26.IGND vs. Temperature
TPC 21.RMS Noise vs. COUT
TPC 24.LDO8 PSRR
ADP3502
THEORY OF OPERATION
As illustrated in the Functional Block Diagram, the ADP3502
can be divided into two high level blocks—analog and logic.
The analog block consists mainly of LDO regulators, a battery
charger, reference voltage, and voltage detector subblocks, all of
which are powered by the main battery or the charging adapter.
On the other hand, VBAT powers all the logic subblocks
except the RTC counter, 32 kHz output control, RESET
output, and stay-alive timer. The RTCV pin powers these
subblocks (see the shaded area of Figure 2).
ANALOG BLOCKS
Low Drop-Out (LDO) Regulators
There are four sub-LDOs for LDO1, LDO2, LDO3, and LDO6,
in order to meet low power consumption at light load (standby
operation). They are used at low load condition, but they are
continuously on even if each of the main LDOs are on. LDO3 and
LDO3b are used for the coin cell, and LDO3b is always on until
the main battery (VBAT) is decreased to 2.5V, the DDLO
threshold. LDO7 and LDO9 are gated by a control signal
from SLEEP or register setting of SLEEP7/SLEEP9. LDO4 and
LDO11 are initially on. For details of LDO on/off control, refer
to the LDO Control section.
Figure 2.Power Partitioning of Subblocks
Table I.Ground Currents of LDOs with Each Handset Operation
Table II.LDO Operation Overview
Figure 3.Battery Charger Block Diagram
ADP3502
Figure 4.Charger Flow Chart A

Partno	Mfg	Dc	Qty	Available	Descript
ADP3502ASU-REEL \|ADP3502ASUREEL	AD	N/a	3158	avai	CDMA Power Management System