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ADP3422JRU-REEL
IMVP-II Compliant Core Controller for Mobile CPUs
REV.0
IMVP-II-Compliant
Core Power Controller for Mobile CPUs
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Certified IMVP-II Controller
Excellent Transient Containment
Minimum Number of Output Capacitors
Fast, Smooth, Output Transition During VID Code Change
Current Limit with Hiccup Protection
Transient-Glitch-Free Power Good
Low Shutdown Current
Soft Start Eliminates In-Rush Current Surge
Adaptive Noise-Blanking Enhancement for Speed and
Stability
Highly Redundant Over-Voltage and Reverse-Voltage
Protection
Controls Synchronous Rectifier for Improved Battery Life
APPLICATIONS
IMVP-II Enabled Core DC/DC Converters
Fixed-Voltage Mobile CPU Core DC/DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
GENERAL DESCRIPTIONThe ADP3422 is a hysteretic dc-dc buck converter controller to
power a mobile processor’s core. The optimized low voltage
design is powered from the 3.3 V system supply. The output
voltage is set by a 5-bit VID code. To accommodate the transition
time required by the newest processors for on-the-fly VID
changes, the ADP3422 features high-speed operation to allow a
minimized inductor size that results in the fastest change of
current to the output. To further allow for the minimum number
of output capacitors to be used, the ADP3422 features active
voltage positioning that can be optimally compensated to ensure a
superior load transient response. The output signal interfaces
with the ADP3415 MOSFET driver that is optimized for high
speed and high efficiency for driving both the upper and lower
(synchronous) MOSFETs of the buck converter.
ADP3422–SPECIFICATIONS
(0 ≤ TA ≤ 85�C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB = VDAC
(� VDACOUT), VREG = VCS– = VVID = 1.25 V, VCPUSET = 0 V, ROUT = 100k�, COUT = 10 pF, CSS = 47 nF, RPWRGD = 5 k� to VCC, RCLAMP = 5.1 k�
to VCC, HYSSET, BSHIFT, DSHIFT, and FSHIFT are open, BOM = H, DSLP = H, DPRSLP = L, SWFB = L, unless otherwise noted. Current sunk
by a pin has a positive sign, sourced by a pin has a negative sign.)
ELECTRICAL CHARACTERISTICS1VID DAC
ADP3422SHIFT CONTROL INPUTS
CURRENT LIMIT COMPARATOR
ADP3422–SPECIFICATIONSNOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Two test conditions:
1. PWRGD is OK but forced to fail by applying an out-of-the-CoreGood-window voltage (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) to the COREFB pin right
after the moment that BOM or DPRSLP is asserted/deasserted. PWRGD should not fail immediately, only with the specified blanking delay time.
2. PWRGD is forced to fail (VCOREFB,BAD = 1.0 V at VVID = 1.25 V setting) but gets into the CoreGood-window (VCOREFB,GOOD = 1.25 V) right after the moment that
BOM or DPRSLP is asserted/deasserted. PWRGD should not go high immediately, only with the specified blanking delay time.Guaranteed by characterization.Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value.40 mV p-p amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing.Measured between the 30% and 70% points of the output voltage swing.
Specifications subject to change without notice.
(continued)
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3422 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3 V to +7 V
UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . –0.3 V to (VCC + 0.3 V)
Operating Ambient Temperature Range . . . . . . . 0°C to 85°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device tobe permanently damaged.
ORDERING GUIDE
PIN CONFIGURATION
ADP3422
PIN FUNCTION DESCRIPTIONS
ADP3422
