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ADP3421ADN/a7avaiGeyserville-Enabled DC/DC Converter Controller for Mobile CPUs


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ADP3421
Geyserville-Enabled DC/DC Converter Controller for Mobile CPUs
REV. A
Geyserville-Enabled DC-DC
Converter Controller for Mobile CPUs
FEATURES
Meets Intel® Mobile Voltage Positioning Requirements
Lowest Processor Dissipation for Longest Battery Life
Best Transient Containment
Minimum Number of Output Capacitors
System Power Management Compliant
Fast, Smooth Output Transition During VID Code
Change
Programmable Current Limit
Power Good
Integrated LDO Controllers for Clock and I/O Supplies
Programmable UVLO
Soft Start with Restart Lock-In
APPLICATIONS
Geyserville-Enabled Core DC-DC Converters
Fixed Voltage Mobile CPU Core DC-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
GENERAL DESCRIPTION

The ADP3421 is a hysteretic dc-dc buck converter controller
with two auxiliary linear regulator controllers. The ADP3421
provides a total power conversion control solution for a micro-
processor by delivering the core, I/O, and clock voltages. The
optimized low-voltage design is powered from the 3.3V system
supply and draws only 10 µA maximum in shutdown. The main
output voltage is set by a 5-bit VID code. To accommodate the
transition time required by the newest processors for on-the-
fly VID changes, the ADP3421 features high-speed operation
to allow a minimized inductor size that results in the fastest change
of current to the output. To further allow for the minimum
number of output capacitors to be used, the ADP3421 features
active voltage positioning that can be optimally compensated
to ensure a superior load transient response. The main output
signal interfaces with the ADP3410 dual MOSFET driver,
which is optimized for high speed and high efficiency for driving
both the upper and lower (synchronous) MOSFETs of the
buck converter.
FUNCTIONAL BLOCK DIAGRAM
ADP3421–SPECIFICATIONS1
(0�C � TA � 100�C, VCC = 3.3V, VSD = VCC, VULVO = 2.0V, VCORE = VDAC, ROUT = 100
k�, COUT = 10 pF, CSSC = 1.8 nF, CSSL = 1.3 nF, CLTB = 1.5 nF, unless otherwise noted.)
ADP3421
LINEAR REGULATOR SOFT-START TIMER
LEVEL TRANSLATOR
NOTESVCORE ramps up monotonically.VCORE ramps down monotonically.During latency time of VID code change, the Power Good output signal should not be considered valid.Internal bias and soft start are not enabled unless the soft-start pin voltage first drops below the enable threshold.Measured from 50% of VID code transient amplitude to the point where VDAC settles within ±1% of its steady state value.Guaranteed by characterization.40mV p-p amplitude impulse with 20mV overdrive. Measure from the input threshold intercept point to 50% of the output voltage swing.Measured between the 30% and 70% points of the output voltage swing.The LTO output tied to VCCLT = 2.5V rail through an RLTO = 150 Ω pull-up resistor.
Specifications subject to change without notice.
ADP3421
CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3421 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ABSOLUTE MAXIMUM RATINGS*

Input Supply Voltage (VCC) . . . . . . . . . . . . . . –0.3V to +7V
UVLO Input Voltage . . . . . . . . . . . . . . . . . . . . –0.3V to +7V
All Other Inputs/Outputs . . . . . . . . . . . . . . . . . . VCC + 0.3V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Junction Temperature Range . . . . . . . . . . . . . . . 0°C to 150°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS


TPC 1.Supply Current vs.
Temperature
TPC 4.DAC Output Voltage vs.
Temperature
TPC 7.LDO Drive Current vs.
Temperature
ADP3421–Typical Performance Characteristics

TPC 2.Power Good vs. Relative
Core Voltage Variation
AMBIENT TEMPERATURE – �C
HYSTERESIS CURRENT 20100406080
100

TPC 5.Core Hysteresis Current vs.
Temperature
LOAD CURRENT – A
IO LDO REGULATOR OUTPUT VOLTAGE
100�1m0.01
0.1110

TPC 8.IO LDO DC Load Regulation
TIMING CAPACITANCE – nF
SOFT-START TIME
ms
1000

TPC 3.Soft-Start Time vs. Timing
Capacitance
AMBIENT TEMPERATURE – �C
CURRENT LIMIT THRESHOLD CURRENT 20100406080
–100

TPC 6.Current Limit Threshold
Current vs. Temperature
TPC 9.CLK LDO DC Load
Regulation
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