ADP3419JRM-REEL ,Dual Bootstrapped, High Voltage MOSFET Driver with Output DisableGENERAL DESCRIPTION GENERAL APPLICATION CIRCUIT The ADP3419 is a dual MOSFET driver optimized for d ..
ADP3421 ,Geyserville-Enabled DC/DC Converter Controller for Mobile CPUsfeaturesactive voltage positioning that can be optimally compensatedto ensure a superior load trans ..
ADP3421JRU ,Geyserville-Enabled DC-DC Converter Controller for Mobile CPUsGENERAL DESCRIPTIONI/O LDOANDIOFBBIAS ANDCORECONTROLLERPOWER GOODThe ADP3421 is a hysteretic dc-dc ..
ADP3421JRU-REEL ,Geyserville-Enabled DC/DC Converter Controller for Mobile CPUsfeaturesactive voltage positioning that can be optimally compensatedto ensure a superior load trans ..
ADP3421JRU-REEL7 ,Geyserville-Enabled DC/DC Converter Controller for Mobile CPUsGENERAL DESCRIPTIONI/O LDOANDIOFBBIAS ANDCORECONTROLLERPOWER GOODThe ADP3421 is a hysteretic dc-dc ..
ADP3422 ,IMVP-II Compliant Core Controller for Mobile CPUsfeatures activeGNDvoltage positioning that can be optimally compensated to ensure asuperior load tr ..
AK4545VQ , AC97 AUDIO CODEC WITH SRC AND DIT
AK4545VQ , AC97 AUDIO CODEC WITH SRC AND DIT
AK4554VT , Low Power & Small Package 16bit ΔΣ CODEC
AK4560AVQ , 16bit CODEC with ALC and MIC/HP/SPK-Amps
AK4561VQ , 16bit CODEC with built-in ALC and MIC/HP-Amp
AK4562VN , LOW POWER 20BIT CODEC WITH PGA
ADP3419JRM-REEL
Dual Bootstrapped, High Voltage MOSFET Driver with Output Disable
Dual Bootstrapped, High Voltage MOSFET
Driver with Output Disable
Rev. 0
FEATURES
All-in-one synchronous buck driver
One PWM signal generates both drives
Anticross-conduction protection circuitry
Output disable function
Crowbar control
Synchronous override control
Undervoltage lockout
APPLICATIONS
Mobile computing CPU core power converters
Multiphase desk-note CPU supplies
Single-supply synchronous buck converters
Nonsynchronous-to-synchronous drive
conversion
GENERAL DESCRIPTION The ADP3419 is a dual MOSFET driver optimized for driving
two N-channel switching MOSFETs in nonisolated synchro-
nous buck power converters used to power CPUs in portable
computers. The driver impedances have been chosen to provide
optimum performance in multiphase regulators at up to 25 A
per phase. The high-side driver can be bootstrapped relative to
the switch node of the buck converter and is designed to
accommodate the high voltage slew rate associated with floating
high-side gate drivers.
The ADP3419 includes an anticross-conduction protection
circuit, undervoltage lockout to hold the switches off until the
driver has sufficient voltage for proper operation, a crowbar
input that turns on the low-side MOSFET independently of the
input signal state, and a low-side MOSFET disable pin to
provide higher efficiency at light loads. The SD pin shuts off
both the high-side and the low-side MOSFETs to prevent rapid
output capacitor discharge during system shutdown.
The ADP3419 is specified over the extended commercial
temperature range of 0°C to 100°C, and is available in a 10-lead
MSOP package.
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
BSTVCC
DRVH
DRVL
GND
DRVLSD04620-0-001
Figure 1.
GENERAL APPLICATION CIRCUIT
VDC
VOUT
FROM SYSTEM
ENABLE CONTROL
FROM CONTROLLER
PWM OUTPUT
FROM
CONTROLLER
FROM CONTROLLER
CLAMP OUTPUT04620-0-002
Figure 2.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Typical Performance Characteristics.............................................7
Theory of Operation........................................................................9
Undervoltage Lockout.................................................................9
Driver Control Input....................................................................9
Low-Side Driver............................................................................9
High-Side Driver..........................................................................9
Overlap Protection Circuit..........................................................9
Low-Side Driver Shutdown.......................................................10
Low-Side Driver Timeout.........................................................10
Crowbar Function......................................................................10
Application Information................................................................11
Supply Capacitor Selection.......................................................11
Bootstrap Circuit........................................................................11
Power and Thermal Considerations........................................11
PC Board Layout Considerations.............................................12
Outline Dimensions.......................................................................13
Ordering Guide..........................................................................13
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS VCC = SD = 5 V, BST = 4 V to 26 V, TA = 0°C to 100°C, unless otherwise noted.
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
Table 1. For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to the signal going low.
2 The turn-on of DRVL is initiated after IN goes low by either SW crossing a ~1 V threshold or by expiration of tSWTO. Guaranteed by characterization, not production tested.
DRVLSD
DRVL
tpdlDRVLSDtpdhDRVLSD
Figure 3. Output Disable Timing Diagram (Timing is Referenced to the 90% and 10% Points unless Otherwise Noted)
DRVL
DRVH-SW
tpdlDRVL04620-0-004
Figure 4. Nonoverlap Timing Diagram (Timing is Referenced to the 90% and 10% Points unless Otherwise Noted)
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Unless otherwise specified, all voltages are referenced to GND.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DRVLSD
CROWBAR
VCC
BST
DRVH
GND
DRVL04620-0-018
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS Figure 6. DRVH Rise and DRVL Fall Times
CH1 = IN, CH2 = DRVH, CH3 = DRVL
Figure 7. DRVH Fall and DRVL Rise Times
CH1 = IN, CH2 = DRVH, CH3 = DRVL
TIME (ns)
JUNCTION TEMPERATURE (°C)25507510012504620-0-007
TIME (ns)
JUNCTION TEMPERATURE (°C)25507510012504620-0-008
Figure 9. DRVL Rise and Fall Times vs. Temperature
ISE TIM
E (
LOAD CAPACITANCE (nF)04620-0-009
108642Figure 10. DRVH and DRVL Rise Times vs. Load Capacitance
FALL TIME (ns)
LOAD CAPACITANCE (nF)0108642
TIME (ns)
JUNCTION TEMPERATURE (°C)25507510012504620-0-011
Figure 12. DRVH and DRVL tpdh vs. Temperature
TIME (ns)
JUNCTION TEMPERATURE (°C)25507510012504620-0-012
Figure 13. DRVH and DRVL tpdl vs. Temperature
AK INP
T CURRE
NT (
INPUT VOLTAGE (V)234504620-0-013
Figure 14. IN Pin Input Current vs. Input Voltage
20040060080010001200
ISYS
CURRE
NT (mA)
IN FREQUENCY (kHz)04620-0-014
Figure 15. Supply Current vs. Frequency
SYS
CURRE
NT (mA)
JUNCTION TEMPERATURE (°C)25507510012504620-0-015
Figure 16. Supply Current vs. Temperature
