ADP3415LRMZ-REEL ,Dual MOSFET Driver with BootstrappingSPECIFICATIONS unless otherwise noted.)Parameter Symbol Conditions Min Typ Max UnitSUPPLY (VCC)2Qui ..
ADP3415LRMZ-REEL ,Dual MOSFET Driver with BootstrappingGENERAL DESCRIPTION5V VThe ADP3415 is a dual MOSFET driver optimized for driving DCINtwo N-channel ..
ADP3416JR ,Dual Bootstrapped MOSFET DriverSpecifications subject to change without notice.–2– REV. AADP3416ABSOLUTE MAXIMUM RATINGS* ORDERING ..
ADP3416JR-REEL ,Dual Bootstrapped MOSFET DriverSPECIFICATIONSAParameter Symbol Conditions Min Typ Max UnitSUPPLYSupply Voltage Range VCC 4.15 7.5 ..
ADP3416JR-REEL ,Dual Bootstrapped MOSFET DriverGENERAL DESCRIPTION high voltage slew rate associated with “floating” high sideThe ADP3416 is a dua ..
ADP3417JR ,Dual Bootstrapped MOSFET DriverSpecifications subject to change without notice.–2– REV. AADP3417*ABSOLUTE MAXIMUM RATINGS ORDERING ..
AK4522VF , 20BIT STEREO ADC & DAC
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ADP3415LRM-REEL-ADP3415LRMZ-REEL
Dual MOSFET Driver with Bootstrapping
REV.B
Dual MOSFET Driver
with Bootstrapping
FEATURES
All-in-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross Conduction Protection Circuitry
Programmable Transition Delay
Zero-Crossing Synchronous Drive Control
Synchronous Override Control
Undervoltage Lockout
Shutdown Quiescent Current <100 �A
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTIONThe ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the nonisolated
synchronous buck power converter topology. Each driver size is
optimized for performance in notebook PC regulators for CPUs
in the 20 A range. The high-side driver can be bootstrapped atop
the switched node of the buck converter as needed to drive the
upper switch and is designed to accommodate the high voltage
slew rate associated with high performance, high frequency
switching. The ADP3415 features an overlapping protection
circuit (OPC); undervoltage lockout (UVLO) that holds the
switches off until the driver is assured of having sufficient voltage
for proper operation; a programmable transition delay; and a
synchronous drive disable pin. The quiescent current, when the
device is disabled, is less than 100µA.
The ADP3415 is specified over the extended commercial
temperature range of 0°C to 100°C and is available in a 10-lead
MSOP package.
Figure 1. Typical Application Circuit
ADP3415–SPECIFICATIONS1(TA = 0�C to 100�C, VCC = 5 V, VBST – VSW = 5 V, SD = 5 V, CDRVH = CDRVL = 3 nF,
unless otherwise noted.)LOW-SIDE DRIVER SHUTDOWN
(DRVLSD)
SHUTDOWN (SD)
INPUT (IN)
THERMAL SHUTDOWN (THSD)
HIGH-SIDE DRIVER (DRVH)
LOW-SIDE DRIVER (DRVL)
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Including IBSTQ quiescent current.The signal source driving the pin must have 70 µA (typ) pull-down strength to make a high-to-low transient, and 20 µA (typ) pull-up strength to make a low-to-high
transient. The pin does not represent load (<100 nA) in static low (<0.8 V) and static high (>2.0 V) logic states (see TPC 3.) The pin can be driven with standard
TTL logic level source.Guaranteed by characterization.For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.Propagation delay measured until DRVL begins its transition.The turn-on of DRVL is initiated after IN goes low by either VSW crossing a ~1.6 V threshold or by expiration of tSWTO.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V
SD, IN, DRVLSD to GND . . . . . . . . . . . . . . –0.3 V to +7.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Operating Junction Temperature Range . . . . . .0°C to 125°C
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
�JC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
PIN CONFIGURATION
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
PIN FUNCTION DESCRIPTIONS7GND
8SWThis pin should be connected to the buck switching node, close to the upper FET’s source. It is the
ORDERING GUIDE*Z = Pb-free part.
ADP3415Figure 2. Functional Block Diagram
Figure 3. DRVLSD Propagation Delay
Figure 4. Switching Timing Diagram (Propagation Delay Referenced to 50%, Rise and Fall Time to 10% and 90% Points)
Figure 5. Switching Waveforms–SW Node Failure Mode–DRVL Timeout
ADP3415–Typical Performance CharacteristicsTPC 1. DRVH Fall and DRVL Rise Times
TPC 2. DRVL Fall and DRVH Rise Times
TPC 3. Input Voltage vs. Input Current
TPC 4. DRVL Rise and Fall Times vs. Temperature
TPC 5. DRVH Rise and Fall Times vs. Temperature
TPC 6. DRVH and DRVL Rise Time vs. Load Capacitance
