ADP3415KRM-REEL ,Dual MOSFET Driver with BootstrappingSpecifications subject to change without notice.REV. PrA–2–PRELIMINARY TECHNICAL DATAADP3415PIN FUN ..
ADP3415KRM-REEL7 ,Dual MOSFET Driver with Bootstrappingfeatures: anDLY DRVLoverlapping protection circuit (OPC) undervoltage lockout (UVLO)GNDthat holds t ..
ADP3415KRM-REEL7 ,Dual MOSFET Driver with BootstrappingSpecifications subject to change without notice.REV. PrA–2–PRELIMINARY TECHNICAL DATAADP3415PIN FUN ..
ADP3415LRM-REEL ,Dual MOSFET Driver with Bootstrappingfeatures an overlapping protectionSTATE LOGICcircuit (OPC); undervoltage lockout (UVLO) that holds ..
ADP3415LRM-REEL ,Dual MOSFET Driver with BootstrappingSpecifications subject to change without notice.–2– REV. BADP3415ABSOLUTE MAXIMUM RATINGS* PIN CONF ..
ADP3415LRM-REEL7 , Dual MOSFET Driver with Bootstrapping
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ADP3415KRM-REEL
Dual MOSFET Driver with Bootstrapping
REV.PrA
PRELIMINARY TECHNICAL DATA
Dual MOSFET Driver
with Bootstrapping
FUNCTIONAL BLOCK DIAGRAM
FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Zero-Crossing Synchronous Drive Control
Synchronous Override Control
Undervoltage Lockout
Shutdown Quiescent Current < 10 mA
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTIONThe ADP3415 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the noniso-
lated synchronous buck power converter topology. The driver
sizes are each optimized for performance in notebook PC regula-
tors for CPUs in the 20-amp range. The high-side driver can be
bootstrapped atop the switched node of the buck converter as
needed to drive the upper switch, and is designed to accommo-
date the high voltage slew-rate associated with high-performance
high-frequency switching. The ADP3415 has several features: an
overlapping protection circuit (OPC) undervoltage lockout (UVLO)
that holds the switches off until the driver is assured of having
sufficient voltage for proper operation, a programmable transition
delay, and a synchronous drive disable pin. The quiescent
current, when the device is disabled, is less than 100mA.
The ADP3415 is available in a 10-lead MSOP package.
Figure 1.Typical Application Circuit
PRELIMINARY TECHNICAL DATA
ADP3415–SPECIFICATIONS1(TA = 0�C to 100�C, VCC = 5 V, VBST = 4 V to 26 V, SD = 5 V, unless otherwise noted.)SHUTDOWN (SD)
INPUT (IN)
THERMAL SHUTDOWN(THSD)
DRVH TURN-ON DELAY TIMER
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
2Logic inputs meet typical CMOS I/O conditions for source current larger than 100 µA.
3Guaranteed by characterization.
4For propagation delays, “tpdh” refers to the specified signal going high, “tpdl” refers to it going low.
5Propagation delay measured until DRVL begins its transition.
6The turn-on of DRVL is initiated after IN goes low by either VSW crossing a ~1 V threshold or by expiration of tSWTO.
7This delay represents a programmable extension to the propagation delay of DRVH assertion (tPDH DRVH). The additional delay is a linear function of the range
0 ≤ RDLY ≤ 100 kΩ delay resistor tied from DLY to GND if its value is the specified resistance.
8The DLY pin may be grounded for no additional delay.
Specifications subject to change without notice.
PRELIMINARY TECHNICAL DATA
ADP3415
PIN FUNCTION DESCRIPTIONS
ORDERING GUIDEADP3415KRM-Reel7
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3415 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
ABSOLUTE MAXIMUM RATINGS*VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
BST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V
SD, IN, DRVLSD to GND . . . . . . . . . . . . . –0.3 V to +7.3 V
Operating Ambient Temperature Range . . . . . . 0°C to 100°C
Operating Junction Temperature Range . . . . . .0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40°C/W
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN CONFIGURATION
10-Lead Mini_SO Package (MSOP)
(RM-10)
PRELIMINARY TECHNICAL DATA
ADP3415Figure 2.Functional Block Diagram
Figure 3.DRVLSD Propagation Delay
PRELIMINARY TECHNICAL DATATPC 1.DRVH Fall and DRVL Rise Times
TPC 2.DRVL Fall and DRVH Rise Times
TPC 3.Input Voltage vs. Input Current
TPC 4.DRVL Rise and Fall Times vs. Temperature
TPC 5.DRVH Rise and Fall Time vs. Temperature
TPC 6.DRVH and DRVL Rise Time vs. Load Capacitance
PRELIMINARY TECHNICAL DATA
ADP3415TPC 7.DRVH and DRVL Propagation
Delay vs. Temperature
TPC 8.DRVH and DRVL Fall Time vs. Load Capacitance
TPC 9.tPDH DRVH vs. Temperature
TPC 10.Current vs. Frequency
TPC 11.Current vs. Temperature
