ADP3415KRM-REEL7 ,Dual MOSFET Driver with Bootstrappingfeatures: anDLY DRVLoverlapping protection circuit (OPC) undervoltage lockout (UVLO)GNDthat holds t ..
ADP3415KRM-REEL7 ,Dual MOSFET Driver with BootstrappingSpecifications subject to change without notice.REV. PrA–2–PRELIMINARY TECHNICAL DATAADP3415PIN FUN ..
ADP3415LRM-REEL ,Dual MOSFET Driver with Bootstrappingfeatures an overlapping protectionSTATE LOGICcircuit (OPC); undervoltage lockout (UVLO) that holds ..
ADP3415LRM-REEL ,Dual MOSFET Driver with BootstrappingSpecifications subject to change without notice.–2– REV. BADP3415ABSOLUTE MAXIMUM RATINGS* PIN CONF ..
ADP3415LRM-REEL7 , Dual MOSFET Driver with Bootstrapping
ADP3415LRMZ-REEL ,Dual MOSFET Driver with BootstrappingSPECIFICATIONS unless otherwise noted.)Parameter Symbol Conditions Min Typ Max UnitSUPPLY (VCC)2Qui ..
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ADP3415KRM-REEL-ADP3415KRM-REEL7
Dual MOSFET Driver with Bootstrapping
Specifications subject to change without notice.REV. PrA–2–PRELIMINARY TECHNICAL DATAADP3415PIN FUNCTION DESCRIPTIONSPin Mnemonic Function1 IN TTL-Level Input Signal. Has primary control of the drive outputs.2 SD Shutdown. When high, this pin enables normal operation. When low, DRVH and DRVL are forced lowand the supply current (I ) is minimized as specified.CCQ)3 DRVLSD Drive-Low Shutdown. When DRVLSD is low, DRVL is kept low. When DRVLSD is high, DRVL isenabled and controlled by IN and by the adaptive OPC function.4 DLY High-Side Turn-On Delay. A resistor from this pin to ground programs an extended delay from turn-offof the lower FET to turn-on of the upper FET.5 VCC Input Supply. This pin should be bypassed to GND with ~10 µ F ceramic capacitor.6 DRVL Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) FET.7 GND Ground. Should be directly connected to the ground plane, close to the source of the lower FET.8 SW This pin should be connected to the buck switching node, close to the upper FET’s source. It is thefloating return for the upper FET drive signal. Also, it is used to monitor the switched voltage for theOPC function.9 DRVH Buck Drive. Output drive for the upper (buck) FET.10 BST Floating Bootstrap Supply for the Upper FET. A capacitor connected between BST and SW pins holdsthis bootstrapped supply voltage for the high-side FET driver as it is switched. The capacitor should be aMLC type and should have substantially greater capacitance (e.g., ~20) than the input capacitance ofthe upper FET.ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATIONVCC to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 VBST to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V10-Lead Mini_SO Package (MSOP)BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V(RM-10)SW to GND . . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 VSD, IN, DRVLSD to GND . . . . . . . . . . . . . –0.3 V to +7.3 VOperating Ambient Temperature Range . . . . . . 0°C to 100°C1 10 BSTINOperating Junction Temperature Range . . . . . . 0°C to 125°C2 ADP3415 9 DRVHSDTOP VIEWθ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/WJA 38 SWDRVLSD(Not to Scale)θ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/WJCDLY 4 7GNDStorage Temperature Range . . . . . . . . . . . . –65°C to +150°CVCC 5 6DRVLLead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C*This is a stress rating only; operation beyond these limits can cause the device tobe permanently damaged.ORDERING GUIDETemperature Package PackageModel Range Description OptionADP3415KRM-Reel 0°C to 100°C Mini_SO Package RM-10MSOP-10)ADP3415KRM-Reel7 0°C to 100°C Mini_SO Package RM-10(MSOP-10)CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyWARNING!accumulate on the human body and test equipment and can discharge without detection. Althoughthe ADP3415
