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ADP3412JR-REEL-ADP3412JR-REEL7
High Speed Synchronous MOSFET Driver
REV.A
Dual MOSFET Driver
with Bootstrapping
FUNCTIONAL BLOCK DIAGRAM
VCCBST
DRVH
DRVL
PGND
DLY
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High Side Drive
One PWM Signal Generates Both Drives
Programmable Transition Delay
Anticross-Conduction Protection Circuitry
APPLICATIONS
Multiphase Desktop CPU Supplies
Mobile Computing CPU Core Power Converters
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter AdaptationsFigure 1.General Application Circuit
GENERAL DESCRIPTIONThe ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs which are the two switches in a
nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000pF load with a 20ns propa-
gation delay and a 30ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage
slew rate associated with “floating” high side gate drivers. The
ADP3412 includes overlapping drive protection (ODP) to pre-
vent shoot-through current in the external MOSFETs.
ADP3412–SPECIFICATIONS1NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 µA).AC specifications are guaranteed by characterization but not production tested.For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.Maximum propagation delay = 40 ns + (1 ns/pF � CDLY).
Specifications subject to change without notice.
(TA = 0�C to 70�C, VCC = 5 V, BST = 4 V to 26 V, unless otherwise noted.)
ABSOLUTE MAXIMUM RATINGS*VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5.0 V to +25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature Range . . . . . . 0°C to 125°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155°C/W
θJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to PGND.
PIN FUNCTION DESCRIPTIONS7SW
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3412 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ADP3412Figure 2.Nonoverlap Timing Diagram
(Timing Is Referenced to the 90% and 10% Points Unless Otherwise Noted)
TPC 1.DRVH Fall and DRVL Rise
Times
AMBIENT TEMPERATURE – �C8525
TIME – ns75TPC 4.DRVL Rise and Fall Times vs.
Temperature
JUNCTION TEMPERATURE – �C25
TIME – ns75
100125TPC 7.Propagation Delay vs.
Temperature
TPC 2.DRVL Fall and DRVH Rise
Times
CAPACITANCE – nF61
TIME – ns
2345TPC 5.DRVH and DRVL Rise Times
vs. Load Capacitance
IN FREQUENCY – kHz
SUPPLY CURRENT – mA12002004006008001000TPC 8.Supply Current vs.
Frequency
TPC 3.DRVH Rise and Fall Times vs.
Temperature
CAPACITANCE – nF
TIME – ns
123456TPC 6.DRVH and DRVL Fall Times
vs. Load Capacitance
JUNCTION TEMPERATURE – �C
SUPPLY CURRENT – mA75100
9.5TPC 9.Supply Current vs.
Temperature
ADP3412
THEORY OF OPERATIONThe ADP3412 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high side and the low side FETs. Each driver
is capable of driving a 3 nF load with only a 20 ns transition time.
A more detailed description of the ADP3412 and its features
follows. Refer to the General Application Circuit in Figure 1.
Low Side DriverThe low side driver is designed to drive low RDS(ON) N-channel
MOSFETs. The maximum output resistance for the driver isΩ for both sourcing and sinking gate current. The low output
resistance allows the driver to have 20 ns rise and fall times into
a 3 nF load. The bias to the low side driver is internally con-
nected to the VCC supply and PGND.
The driver’s output is 180 degrees out of phase with the PWM
input.
High Side DriverThe high side driver is designed to drive a floating low RDS(ON)
N-channel MOSFET. The maximum output resistance for the
driver is 5 Ω for both sourcing and sinking gate current. The
low output resistance allows the driver to have 20 ns rise and fall
times into a 3 nF load. The bias voltage for the high side driver
is developed by an external bootstrap supply circuit, which is
connected between the BST and SW Pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST. When the ADP3412 is starting up, the SW Pin
is at ground, so the bootstrap capacitor will charge up to VCC
through D1. When the PWM input goes high, the high side
driver will begin to turn ON the high side MOSFET, Q1, by
pulling charge out of CBST. As Q1 turns ON, the SW Pin will
rise up to VIN, forcing the BST Pin to VIN + VC(BST), which is
enough gate-to-source voltage to hold Q1 ON. To complete the
cycle, Q1 is switched OFF by pulling the gate down to the volt-
age at the SW Pin. When the low side MOSFET, Q2, turns
ON, the SW Pin is pulled to ground. This allows the bootstrap
capacitor to charge up to VCC again. The high side driver’s
output is in phase with the PWM input.
Overlap Protection CircuitThe overlap protection circuit (OPC) prevents both of the
main power switches, Q1 and Q2, from being ON at the same
time. This is done to prevent shoot-through currents from flow-
ing through both power switches and the associated losses that
can occur during their ON-OFF transitions. The overlap pro-
tection circuit accomplishes this by adaptively controlling the
delay from Q1’s turn OFF to Q2’s turn ON and by externally
setting the delay from Q2’s turn OFF to Q1’s turn ON.
To prevent the overlap of the gate drives during Q1’s turn OFF
and Q2’s turn ON, the overlap circuit monitors the voltage at
the SW Pin. When the PWM input signal goes low, Q1 will begin
to turn OFF (after a propagation delay), but before Q2 can turn
ON, the overlap protection circuit waits for the voltage at the SW
Pin to fall from VIN to 1 V. Once the voltage on the SW Pin has
fallen to 1 V, Q2 will begin turn ON. By waiting for the voltage
on the SW Pin to reach 1 V, the overlap protection circuit ensures
To prevent the overlap of the gate drives during Q2’s turn OFF
and Q1’s turn ON, the overlap circuit provides a programmable
delay that is set by a capacitor on the DLY Pin. When the PWM
input signal goes high, Q2 will begin to turn OFF (after a propa-
gation delay), but before Q1 can turn ON, the overlap protection
circuit waits for the voltage at DRVL to drop to around 10% of
VCC. Once the voltage at DRVL has reached the 10% point,
the overlap protection circuit will wait for a 20 ns typical propa-
gation delay plus an additional delay based on the external
capacitor, CDLY. The delay capacitor adds an additional 1 ns/pF
of delay. Once the programmable delay period has expired, Q1
will begin turn ON. The delay allows time for current to com-
mutate from the body diode of Q2 to an external Schottky diode,
which allows turnoff losses to be reduced. Although not as fool-
proof as the adaptive delay, the programmable delay adds a
safety margin to account for variations in size, gate charge, and
internal delay of the external power MOSFETs.
APPLICATION INFORMATION
Supply Capacitor SelectionFor the supply input (VCC) of the ADP3412, a local bypass
capacitor is recommended to reduce the noise and to supply some
of the peak currents drawn. Use a 1µF, low ESR capacitor.
Multilayer ceramic chip (MLCC) capacitors provide the best
combination of low ESR and small size and can be obtained from
the following vendors:
Murata GRM235Y5V106Z16 www.murata.com
Taiyo-
Yuden EMK325F106ZF www.t-yuden.com
Tokin C23Y5V1C106ZP www.tokin.com
Keep the ceramic capacitor as close as possible to the ADP3412.
Bootstrap CircuitThe bootstrap circuit uses a charge storage capacitor (CBST) and
a Schottky diode, as shown in Figure 1. Selection of these com-
ponents can be done after the high side MOSFET has been
chosen.
The bootstrap capacitor must have a voltage rating that is able
to handle the maximum battery voltage plus 5 V. A minimum
50 V rating is recommended. The capacitance is determined
using the following equation:
where, QGATE is the total gate charge of the high side MOSFET,
and ∆VBST is the voltage droop allowed on the high side MOSFET
drive. For example, the IRF7811 has a total gate charge of about
20 nC. For an allowed droop of 200 mV, the required boot-
strap capacitance is 100 nF. A good quality ceramic capacitor
should be used.
A Schottky diode is recommended for the bootstrap diode due
to its low forward drop, which maximizes the drive available for
the high side MOSFET. The bootstrap diode must have a mini-
mum 40 V rating to withstand the maximum battery voltage
plus 5 V. The average forward current can be estimated by:
