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ADP3410KRU-REEL-ADP3410KRU-REEL7
Dual MOSFET Driver with Bootstrapping
REV. A
Dual MOSFET Driver
with Bootstrapping
FEATURES
All-In-One Synchronous Buck Driver
One PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Programmable Transition Delay
Synchronous Override Control
Undervoltage Lockout
Programmable Overvoltage Shutdown
VCC Good Signal Drives Auxiliary Circuits
Shutdown Quiescent Current < 10 �A
APPLICATIONS
Mobile Computing CPU Core Power Converters
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
Standard-to-Synchronous Converter Adaptations
GENERAL DESCRIPTIONThe ADP3410 is a dual MOSFET driver optimized for driving
two N-channel FETs that are the two switches in the non-
isolated synchronous buck power converter topology. Each of
the drivers is capable of driving a 3000pF load with a 20ns
propagation delay and a 30ns transition time. One of the drivers
can be bootstrapped, and is designed to handle the high-voltage
slew rate associated with “floating” high-side gate drivers. The
ADP3410 has several protection features: overlapping drive
prevention (ODP), undervoltage lockout (UVLO) with perform-
ance specified at very low VCC levels, and overvoltage protection
(OVP) that can be used to monitor either the input or output.
Additional features include: programmable transition delay, a
synchronous drive override control pin, a synchronous drive
status monitor and, in conjunction with exiting from the UVLO
mode, a VCC Good (VCCGD) signal capable of driving a 10mA
load. The quiescent current, when the device is disabled, is less
than 10mA.
Figure 1.Typical Application Circuit
FUNCTIONAL BLOCK DIAGRAM
ADP3410–SPECIFICATIONS1SYNCHRONOUS RECTIFIER
UNDERVOLTAGE LOCKOUT
HIGH-SIDE DRIVER
(TA = 0�C to 85�C, VCC = 5 V, VBST = 4 V to 26 V, SD > 2 V, unless otherwise
noted.)
ADP3410NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.AC specifications are guaranteed by characterization, but not production tested.For propagation delays, tpdh refers to the specified signal going high, tpdl refers to it going low.Propagation delay measured until DRVL begins its transition.Logic inputs meet typical CMOS I/O conditions for source/sink current (~1 mA).Maximum propagation delay = 40 ns max + (1 ns/pF ¥ CDLY).
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*VCC to PGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
BST to PGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +30 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
SW to PGND . . . . . . . . . . . . . . . . . . . . . . . . –2.0 V to +25 V
OVPSET to PGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +10 V
SD, IN, DRVLSD to GND . . . . . . . . . . . . . . –0.3 V to +7.3 V
GND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3 V
Operating Ambient Temperature Range . . . . . . . 0∞C to 85∞C
Operating Junction Temperature Range . . . . . . 0∞C to 125∞CqJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155∞C/WqJC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40∞C/W
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300∞C
*This is a stress rating only; operation beyond these limits can cause the device tobe permanently damaged.
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3410 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
ADP3410
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
10%
SRMON
GND
VBATT
CDLY
VCCGD
DLY
OVPSET
DRVLSDVOUTFigure 2.Functional Block Diagram
Figure 3.DRVLSD Propagation Delay
ADP3410Figure 4.VCCGD Propagation Delay
Figure 5.UVLO Propagation Delay
Figure 6.Nonoverlap Timing Diagram
