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ADP3333ARM-1.5-RL7-ADP3333ARM-1.8RL7-ADP3333ARM-3.15-RL-ADP3333ARM-3.3-RL7-ADP3333ARMZ-1.8RL7
High Accuracy Ultralow IQ, 300 mA, anyCAP® Low Dropout Regulator
REV.A
High Accuracy Ultralow IQ, 300 mA,
anyCAP® Low Dropout Regulator
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Accuracy over Line and Load: �0.8% @ 25�C,�1.8% Over Temperature
Ultralow Dropout Voltage: 230 mV (Max) @ 300 mA
Requires Only CO = 1.0 �F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: < 1 �A
2.6 V to 12 V Supply Range
–40�C to +85�C Ambient Temperature Range
Ultrasmall 8-Lead MSOP Package
APPLICATIONS
Cellular Phones
PCMCIA Cards
Personal Digital Assistants (PDAs)
DSP/ASIC Supplies
GENERAL DESCRIPTIONThe ADP3333 is a member of the ADP333x family of precision
low dropout (LDO) any CAP voltage regulators. Pin compatible
with the MAX8860, the ADP3333 operates with a wider input
voltage range of 2.6 V to 12 V and delivers a load current up to
300 mA. ADP3333 stands out from other conventional LDOs
with a novel architecture and an enhanced process that enables
it to offer performance advantages over its competition. Its
patented design requires only a 1.0 µF output capacitor for
stability. This device is insensitive to output capacitor
equivalent series resistance (ESR) and is stable with any good
quality capacitor, including ceramic (MLCC) types for space-
restricted applications. The ADP3333 achieves exceptional
accuracy of ±0.8% at room temperature and ±1.8% over
temperature, line, and load variations. The dropout voltage of
the ADP3333 is only 140 mV (typical) at 300 mA. This device
also includes a safety current limit, thermal overload protection,
and a shutdown feature. In shutdown mode, the ground current
is reduced to less than 1µA. The ADP3333 has ultralow
quiescent current, 70 µA (typ) in light load situations.
Figure 1.Typical Application Circuit
ADP3333–SPECIFICATIONS1NOTESApplication stable with no load.VIN = 2.6V for models with VOUTNOM ≤ 2.3V.
Specifications subject to change without notice.
(VIN = 6.0 V, CIN = COUT = 1.0 �F, TJ =–40�C to +125�C, unless otherwise noted.)
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3333 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage . . . . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . . Internally Limited
Operating Ambient Temperature Range . . . . .–40°C to +85°C
Operating Junction Temperature Range . . . .–40°C to +125°C
�JA (4-Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158°C/W
�JA (2-Layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C/W
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
PIN FUNCTION DESCRIPTIONS
ADP3333 TPC 1.Line Regulation Output
Voltage vs. Supply Voltage
TPC 4. Ground Current vs.
Load Current
TPC 7.Dropout Voltage vs.
Output Current
TPC 2. Output Voltage vs.
Load Current
JUNCTION TEMPERATURE – �C
OUTPUT CHANGE – %
–0.4TPC 5.Output Voltage Variation
% vs. Junction Temperature
TPC 8. Power-Up/Power-Down
TPC 3. Ground Current vs.
Supply Voltage
TPC 6. Ground Current vs.
Junction Temperature
TPC 9. Power-Up Response
–Typical Performance Characteristics
TPC 10.Line Transient Response
TPC 13.Load Transient Response
TPC 16.Power Supply Ripple
Rejection
TPC 11.Line Transient Response
TPC 14.Short-Circuit Current
TPC 17. RMS Noise vs. CL
(10Hz to 100kHz)
TPC 12. Load Transient Response
TPC 15. Turn ON-Turn OFF Response
TPC 18.Output Noise Density
ADP3333
THEORY OF OPERATIONThe new anyCAP LDO ADP3333 uses a single control loop for
regulation and reference functions (see Figure 2). The output
voltage is sensed by a resistive voltage divider consisting of R1
and R2 that is varied to provide the available output voltage
option. Feedback is taken from this network by way of a series
diode (D1) and a second resistor divider (R3 and R4) to the
input of an amplifier.
Figure 2.Functional Block Diagram
A very high gain error amplifier is used to control this loop. The
amplifier is constructed in such a way that at equilibrium it pro-
duces a large, temperature-proportional input offset voltage that is
repeatable and very well controlled. The temperature propor-
tional offset voltage is combined with the complementary diode
voltage to form a virtual band gap voltage, implicit in the network,
although it never appears explicitly in the circuit. Ultimately, this
patented design makes it possible to control the loop with only one
amplifier. This technique also improves the noise characteristics
of the amplifier by providing more flexibility on the trade-off of
noise sources and leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to the output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values can be chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the load-
ing of the divider so that the error resulting from base current
loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to include
the load capacitor in a pole splitting arrangement to achieve
reduced sensitivity to the value, type, and ESR of the load
capacitance.
Most LDOs place very strict requirements on the range of ESR
values for the output capacitor because they are difficult to stabilize
due to the uncertainty of load capacitance and resistance. Moreover,
the ESR value required to keep conventional LDOs stable changes
depending on load and temperature. These ESR limitations make
designing with LDOs more difficult because of their unclear
specifications and extreme variations over temperature.
With the ADP3333 anyCAP LDO, this is no longer true. This
device can be used with virtually any good quality capacitor, with
no constraint on the minimum ESR. Its innovative design allows
the circuit to be stable with just a small 1 µF capacitor on the out-
put. Additional advantages of the pole splitting scheme include
superior line noise rejection and very high regulator gain, which
leads to excellent line and load regulation. An impressive ±1.8%
accuracy is guaranteed over line, load, and temperature.
Additional features of the circuit include current limit and ther-
mal shutdown.
APPLICATION INFORMATION
Capacitor Selection
Output CapacitorThe stability and transient response of the LDO is a function of
the output capacitor. The ADP3333 is stable with a wide range
of capacitor values, types, and ESR (anyCAP). A capacitor as
low as 1.0 µF is all that is needed for stability; larger capacitors
can be used if high current surges on the output are anticipated.
The ADP3333 is stable with extremely low ESR capacitors
(ESR ≈ 0), such as multilayer ceramic capacitors (MLCC) or
OSCON. Note that the effective capacitance of some capacitor
types falls below the minimum overtemperature or with dc voltage.
Ensure that the capacitor provides at least 1.0 µF of capaci-
tance over temperature and dc bias.
Input Bypass CapacitorAn input bypass capacitor is not strictly required but is recom-
mended in any application involving long input wires or high
source impedance. Connecting a 1.0 µF capacitor from the input
to ground reduces the circuit’s sensitivity to PC board layout and
input transients. If a larger output capacitor is necessary, then a
larger value input capacitor is also recommended.
Output Current LimitThe ADP3333 is short-circuit protected by limiting the pass
transistor’s base drive current. The maximum output current is
limited to about 1 A (TPC 14).
Thermal Overload ProtectionThe ADP3333 is protected against damage due to excessive power
dissipation by its thermal overload protection circuit. Thermal
protection limits the die temperature to a maximum of 165°C.
Under extreme conditions (i.e., high ambient temperature and
power dissipation) where the die temperature starts to rise above
165°C, the output current will be reduced until the die tempera-
ture has dropped to a safe level.
Current and thermal limit protections are intended to protect
the device against accidental overload conditions. For normal
operation, the device’s power dissipation should be externally
limited so that the junction temperature will not exceed 125°C.
