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ADP3331ART-REEL-ADP3331ART-REEL7-ADP3331ARTZ-REEL7
High Accuracy, Ultra-Low Quiescent Current LDO; SOT-23
REV. A
Adjustable Output Ultralow IQ, 200 mA,
SOT-23, anyCAP Low Dropout Regulator
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Accuracy over Line and Load: �0.7% @ 25�C,
1.4% over Temperature
Ultralow Dropout Voltage: 140 mV (Typ) @ 200 mA
Can Be Used as a High Current (>1 A) LDO
Controller
Requires Only CO = 0.47 �F for Stability
anyCAP = Stable with Any Type of Capacitor
(Including MLCC)
Current and Thermal Limiting
Low Noise
Low Shutdown Current: 10 nA Typical
2.6 V to 12 V Supply Range
1.5 V to 11.75 V Output Range
–40�C to +85�C Ambient Temperature Range
Ultrasmall Thermally Enhanced Chip-on-Lead™
SOT-23-6 Lead Package
APPLICATIONS
Cellular Telephones
Notebook, Palmtop Computers
Battery-Powered Systems
PCMCIA Regulators
Bar Code Scanners
Camcorders, Cameras
GENERAL DESCRIPTIONThe ADP3331 is a member of the ADP330x family of precision
low dropout anyCAP voltage regulators. The ADP3331 operates
with an input voltage range of 2.6 V to 12 V and delivers a load
current up to 200 mA. The ADP3331 stands out from the
conventional LDOs with a novel architecture and an enhanced
process that enables it to offer performance advantages and higher
output current than its competition. Its patented design requires
only a 0.47 mF output capacitor for stability. This device is insensi-
tive to capacitor equivalent series resistance (ESR), and is stable
with any good quality capacitor, including ceramic (MLCC) types
for space restricted applications. The ADP3331 achieves excep-
tional accuracy of ±0.7% at room temperature and ±1.4% overall
accuracy over temperature, line, and load variations. The drop-
out voltage of the ADP3331 is only 140 mV (typical) at 200mA.
This device also includes a safety current limit, thermal over-
load protection, and a shutdown feature. In shutdown mode, the
ground current is reduced to less than 2 mA. The ADP3331 has
ultralow quiescent current 34 mA (typical) in light load situations.
The SOT-23-6 package has been thermally enhanced using
Analog Device’s proprietary Chip-on-Lead feature to maxi-
mize power dissipation.
Figure 1.Typical Application Circuit
ADP3331–SPECIFICATIONS
(TA = –40�C to +85�C, VIN = 7 V, CIN = 0.47 �F, COUT = 0.47 �F, unless otherwise
noted.)1, 2
ADP3331ERROR PIN OUTPUT
NOTESAmbient temperature of 85∞C corresponds to a junction temperature of 125∞C under typical full load test conditions.Application stable with no load.Assumes the use of ideal resistors. Overall accuracy also depends on the tolerance of the external resistors used to set the output voltage.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage . . . . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . .–0.3 V to +16 V
Power Dissipation . . . . . . . . . . . . . . . . . . . .Internally Limited
Operating Ambient Temperature Range . . . .–40∞C to +85∞C
Operating Junction Temperature Range . . .–40∞C to +125∞CqJA(4-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . .165∞C/WqJA(2-Layer Board) . . . . . . . . . . . . . . . . . . . . . . . .190∞C/W
Storage Temperature Range . . . . . . . . . . . .–65∞C to +150∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . .300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . .215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3331 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
ADP3331
–Typical Performance CharacteristicsTPC 1.Line Regulation Output
Voltage vs. Supply Voltage
TPC 4.Ground Current vs. Load
Current
TPC 7.Dropout Voltage vs.
Output Current
TPC 2.Output Voltage vs. Load
Current
JUNCTION TEMPERATURE (�C)
OUTPUT VOLTAGE (%)TPC 5.Output Voltage Variation % vs.
Junction Temperature
TPC 8.Power-Up/Power-Down
TPC 3.Ground Current vs. Supply
Voltage
JUNCTION TEMPERATURE (�C)
GROUND CURRENT (mA)
135TPC 6.Ground Current vs. Junction
Temperature
TPC 9.Power-Up Response
TIME (�s)
OUT
(V)
(V)TPC 10.Line Transient Response
TPC 13.Load Transient Response
FREQUENCY (Hz)
RIPPLE REJECTION (dB)1001k10k100k1M10M
–90TPC 16.Power Supply Ripple
Rejection
TIME (�s)
OUT
(V)
(V)TPC 11.Line Transient Response
TPC 14.Short Circuit Current
TPC 17.RMS Noise vs. CL
(10 Hz to 100 kHz)
TPC 12.Load Transient Response
TPC 15.Turn On–Turn Off Response
TPC 18.Output Noise Density
ADP3331
THEORY OF OPERATIONThe ADP3331 anyCAP LDO uses a single control loop for both
regulation and reference functions, as shown in Figure 2. The
output voltage is sensed by an external resistive voltage divider
consisting of R1 and R2. Feedback is taken from this network
by way of a series diode (D1) and a second resistor divider (R3
and R4) to the input of an amplifier.
Figure 2.Functional Block Diagram
A very high gain error amplifier is used to control this loop.
Theamplifier is constructed in such a way that at equilibrium it
produces a large, temperature-proportional input offset voltage
that is repeatable and very well controlled. The temperature-
proportional offset voltage is combined with the complementary
diode voltage to form a virtual band gap voltage, implicit in the
network, although it never appears explicitly in the circuit. Ulti-
mately, this patented design makes it possible to control the loop
with only one amplifier. This technique also improves the noise
characteristics of the amplifier by providing more flexibility on
the trade-off of noise sources, which leads to a low noise design.
The R1, R2 divider is chosen in the same ratio as the band gap
voltage to output voltage. Although the R1, R2 resistor divider
is loaded by the diode D1 and a second divider consisting of R3
and R4, the values are chosen to produce a temperature stable
output. This unique arrangement specifically corrects for the
loading of the divider so that the error resulting from the base
current loading in conventional circuits is avoided.
The patented amplifier controls a new and unique noninverting
driver that drives the pass transistor, Q1. The use of this special
noninverting driver enables the frequency compensation to
include the load capacitor in a pole-splitting arrangement to
achieve reduced sensitivity to the value, type, and ESR of the
load capacitor.
Most LDOs place strict requirements on the range of ESR values
for the output capacitor because they are difficult to stabilize due
to the uncertainty of the load capacitance and resistance. More-
over, the ESR value required to keep conventional LDOs stable
changes, depending on load and temperature. These ESR limita-
tions make designing with LDOs more difficult because of their
unclear specifications and extreme variations over temperature.
The ADP3331 solves this problem. It can be used with any good
quality capacitor, with no constraint on the minimum ESR. The
innovative design allows the circuit to be stable with just a small
0.47mF capacitor on the output. Additional advantages of the
pole-splitting scheme include superior line noise rejection and
very high regulator gain. The high gain leads to excellent regula-
tion, and ±1.4% accuracy is guaranteed over line, load, and
temperature.
Additional features of the circuit include current limit, thermal
shutdown, and an error flag. Compared to standard solutions that
give a warning after the output has lost regulation, the ADP3331
provides improved system performance by enabling the ERR pin
to give a warning just before the device loses regulation.
As the chip’s temperature rises above +165∞C, the circuit acti-
vates a soft thermal shutdown to reduce the current to a safe
level. The thermal shutdown condition is indicated by the ERR
signal going low.
APPLICATION INFORMATION
Capacitor SelectionOutput Capacitor: The stability and transient response of the
LDO is a function of the output capacitor. The ADP3331 is stable
with a wide range of capacitor values, types, and ESR (anyCAP).
A capacitor as low as 0.47 mF is all that is needed for stability;
larger capacitors can be used if high current surges on the output
are anticipated. The ADP3331 is stable with extremely low ESR
capacitors (ESR ª 0), such as multilayer ceramic capacitors
(MLCC) or OSCON. Note that the effective capacitance of some
capacitor types falls below the minimum over temperature or
with dc voltage.
Input Capacitor: An input bypass capacitor is not strictly required
but is recommended in any application involving long input
wires or high source impedance. Connecting a 0.47mF capacitor
from the input to ground reduces the circuit’s sensitivity toboard layout and input transients. If a larger output capacitor
is necessary, a larger value input capacitor is also recommended.
Noise Reduction Capacitor: A noise reduction capacitor can be
used to reduce the output noise by 6 dB to 10 dB. This capaci-
tor limits the noise gain when connected between the feedback
pin (FB) and the output pin (OUT), as shown in Figure 3. Low
leakage capacitors in the 10 pF to 500 pF range provide the best
performance. Since FB is internally connected to a high imped-
ance node, any connection to this node should be carefully done
to avoid noise pickup from external sources. The pad connected
to this pin should be as small as possible; long PC board traces
are not recommended. When adding a noise reduction capacitor,
use the following guidelines:Maintain a minimum load current of 1 mA when not in
shutdown.For CNR values greater than 500 pF, add a 100 kW series
resistor (RNR).
It is important to note that as CNR increases, the turn-on time
will be delayed. With CNR values greater than 1nF, this delay
may be on the order of several milliseconds.
