ADP3204JCP-REEL ,3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUsfeatures active voltage positioning with ADOPT optimal compensation to ensure a superiorload transi ..
ADP3207CJCPZ-RL , 7-Bit Programmable, Multi-Phase Mobile, CPU Synchronous Buck Controller
ADP3208C ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3208D ,7-Bit, Programmable, Dual-Phase, Mobile, CPU, Synchronous Buck Controller3IMON DPRSLPRPMDPRSTPIREFPSIVID0LLINEVID1CSCOMPVID2CSREFVID3CSSUMVID4RAMPVID5ILIMNVID6ILIMPS PRTVCC ..
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
ADP3209CJCPZ-RL , 5-Bit, Programmable, Single-Phase, Synchronous Buck Controller
AK2500B , DS3/STS-1 Analog Line Receiver
AK2500B , DS3/STS-1 Analog Line Receiver
AK40A-048L-050F03SM , 15 Watts
AK4112A , High Feature 96kHz 24bit DIR
AK4120VF , Sample Rate Converter with Mixer and Volume
AK4121AVF , Asynchronous Sample Rate Converter
ADP3204JCP-REEL
3-Phase IMVP-II and IMVP-III Core Controller for Mobile CPUs
REV. 0
3-Phase IMVP-II and IMVP-III
Core Controller for Mobile CPUsADOPT is a trademark of Analog Devices, Inc.
*.Patent No. 5,969,657; other patents pending.
FEATURES
Pin Selectable 1-, 2-, or 3-Phase Operation
Static and Dynamic Current Sharing Characteristics
Backward Compatible to IMVP-II
Superior Load Transient Response with ADOPT®
Analog Devices’ Optimal Positioning Technology
Noise-Blanking for Speed and Stability
Synchronous Rectifier Control Extends Battery Life
Smooth Output Transition During VID Code Change
Cycle-by-Cycle Current Limiting
Hiccup or Latched Overload Protection
Transient-Glitch-Free Power Good
Soft Start Eliminates Power-On In-Rush Current Surge
Two-Level Overvoltage and Reverse Voltage
Protection
APPLICATIONS
IMVP-II and IMVP-III Core DC-to-DC Converters
Fixed Voltage Mobile CPU Core DC-to-DC Converters
Notebook/Laptop Power Supplies
Programmable Output Power Supplies
FUNCTIONAL BLOCK DIAGRAM
VID0
VID1
VID2
VID3
VID4
DACOUT
GND
VCC
CS+
CS–
REG
COREFB
PWRGD
BOM
DPSLP
HYSSET
BSHIFT
DSHIFT
CLAMP
RAMP
DRVLSD
OUT3
OUT2
CS1
CS2
DPRSHIFT
OUT1
CS3DACRAMP
DPRSLP
GENERAL DESCRIPTIONThe ADP3204 is a 1-, 2-, or 3-phase hysteretic peak current
dc-to-dc buck converter controller dedicated to power a mobile
processor’s core. The optimized low voltage design is powered
from the 3.3 V system supply. The nominal output voltage is
set by a 5-bit VID code. To accommodate the transition time
required by the newest processors, the ADP3204 features
high speed operation to allow a minimized inductor size that
results in the fastest change of current to the output. To
further allow for the minimum number of output capacitors
to be used, the ADP3204 features active voltage positioning
with ADOPT optimal compensation to ensure a superior
load transient response. The output signals interface with a
maximum of three ADP3415 MOSFET drivers that are
optimized for high speed and high efficiency for driving both the
top and bottom MOSFETs of the buck converter. The
ADP3204 is capable of controlling the synchronous rectifiers to
extend battery lifetime in light load conditions.
ADP3204–SPECIFICATIONS1
(0°C � TA � 100°C, High (H) = VCC, Low (L) = 0 V, VCC = 3.3 V, SD = H, VCOREFB =
VDAC (VDACOUT), VREG = VCS– = VVID = 1.25 V, CDACRAMP = 100 pF, ROUT1 = ROUT2 = ROUT3 =
100k�, COUT1 = COUT2 = COUT3 =10 pF, CSS = 0.047 �F, RPWRGD = 680 � to 1.2 V, RCLAMP = 5.1 k� to VCC, HYSSET, BSHIFT, DSHIFT, and
DPRSHIFT are open, BOM = H, DPSLP = H, DPRLP = L, unless otherwise noted.) Current sunk by a pin has a positive sign, sourced by a pin has a
negative sign. Negative sign is disregarded for min and max values.
ADP3204
ADP3204NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Two test conditions: 1) PWRGD is OK but forced to fail by applying an out-of-the-Core Good-window voltage (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) to the
COREFB pin right after the moment that BOM or DPRSLP is asserted/de-asserted. PWRGD should not fail immediately only with the specified blanking delay
time. 2) PWRGD is forced to fail (VCOREFB, BAD = 1.0 V at VVID = 1.25 V setting) but gets into the Core Good-window (VCOREFB, GOOD = 1.25 V) right after the moment
that BOM or DPRSLP is asserted/de-asserted. PWRGD should not go high immediately only with the specified blanking delay time.Guaranteed by design Measured from 50% of VID code transition amplitude to the point where VDACOUT settles within ±1% of its steady state value.Measured between DACRAMP and DACOUT pins. 40 mVpp amplitude impulse with 20 mV overdrive. Measured from the input threshold intercept point to 50% of the output voltage swing. Measured between the 30% and 70% points of the output voltage swing.DPRSLP circuit meets the minimum 30 ns DPRSLPVR signal assertion requirement; guaranteed by design.COREFB pin has a resistor divider to GND whose resistance is 41.3 k� (typ), guaranteed by design.
LOW SIDE DRIVE CONTROL
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage (VCC) . . . . . . . . . . . . . . .–0.3 V to +7 V
All Other Inputs/Outputs . . . . . . . . . . . .–0.3 V to VCC + 0.3 V
Junction Temperature Range . . . . . . . . . . . . . .0°C to +150°C
ORDERING GUIDEJunction to Air Thermal Resistance (θJA) . . . . . . . . . . .98°C/W
Storage Temperature Range . . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
Table I. VID CODE
ADP3204
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
VID4
VID3
VID2
VID1
VID0
BOM
DPSLP
DPRSHIFTBSHIFT
DSHIFT
HYSSETCS+REG
RAMP
CS–
PWRGD
CLAMP
DRVLSD
COREFB
DACRAMP
DACOUT
SS
DPRSLP
VCC
CS3
CS2
CS1
OUT3
OUT2
OUT1
GND
PIN FUNCTION DESCRIPTIONS (continued)18–20
ADP3204
PIN FUNCTION DESCRIPTIONS (continued)
