ADP3188 ,6-Bit Programmable 2-/3-/4-Phase Synchronous Buck ControllerCharacteristics 8 Output Offset...... 17 Theory of Operation 9 C Selection ..... 18 OUTStart-Up S ..
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ADP3188-ADP3188JRUZ-REEL
6-Bit Programmable 2-/3-/4-Phase Synchronous Buck Controller
6-Bit Programmable 2-/3-/4-Phase
Synchronous Buck Controller
FEATURES
Selectable 2-, 3- or 4-phase operation at up to
1 MHz per phase
±9.5 mV worst-case differential sensing error over
temperature
Logic-level PWM outputs for interface to external
high power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
6-bit digitally programmable 0.8375 V to 1.6 V output
Programmable short-circuit protection with
programmable latch-off delay
APPLICATIONS
Desktop PC power supplies for
Next-generation Intel processors
VRM modules
GENERAL DESCRIPTION The ADP3188 is a highly efficient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel® processors. It uses an internal 6-bit DAC to read
a voltage identification (VID) code directly from the processor,
which is used to set the output voltage between 0.8375 V and
1.6 V. It uses a multimode PWM architecture to drive the logic-
level outputs at a programmable switching frequency that can
be optimized for VR size and efficiency. The phase relationship
of the output signals can be programmed to provide 2-, 3-, or
4-phase operation, allowing the construction of up to four
complementary buck switching stages.
The ADP3188 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3188 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output voltage
changes requested by the CPU.
The ADP3188 is specified over the commercial temperature
range of 0°C to 85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND11
DELAY12
ILIMIT15
PWRGD10
RAMPADJ
PWM2FB
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
VID4
VID3
VID2
VID1
VID5
VID0
FBRTN
COMPFigure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Test Circuits.......................................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Description..............................7
Typical Performance Characteristics.............................................8
Theory of Operation........................................................................9
Start-Up Sequence........................................................................9
Master Clock Frequency..............................................................9
Output Voltage Differential Sensing..........................................9
Output Current Sensing..............................................................9
Active Impedance Control Mode.............................................10
Current Control Mode and Thermal Balance........................10
Voltage Control Mode................................................................10
Soft Start......................................................................................10
Current Limit, Short-Circuit, and Latch-Off Protection.......11
Dynamic VID..............................................................................11
Power Good Monitoring...........................................................12
Output Crowbar.........................................................................13
Output Enable and UVLO........................................................13
Application Information................................................................15
Setting the Clock Frequency.....................................................15
Soft Start and Current Limit Latch-Off Delay Times...........15
Inductor Selection......................................................................15
Designing an Inductor...............................................................16
Selecting a Standard Inductor..............................................16
Output Droop Resistance..........................................................16
Inductor DCR Temperature Correction.................................17
Output Offset..............................................................................17
COUT Selection.............................................................................18
Power MOSFETs.........................................................................18
Ramp Resistor Selection............................................................20
COMP Pin Ramp.......................................................................20
Current Limit Setpoint..............................................................20
Feedback Loop Compensation Design....................................20
CIN Selection and Input Current di/dt Reduction..................22
Tuning the ADP3188.................................................................22
DC Loadline Setting..............................................................22
AC Loadline Setting...............................................................23
Initial Transient Setting.........................................................23
Layout and Component Placement.........................................24
General Recommendations..................................................24
Power Circuitry Recommendations....................................24
Signal Circuitry Recommendations....................................24
Outline Dimensions.......................................................................25
Ordering Guide..........................................................................25
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production.
TEST CIRCUITS
12V100nF
100nF
ADP3188Figure 2. Closed-Loop Output Voltage Accuracy
39kΩ
1kΩ
1.0V
12V04835-0-006
Figure 3. Current Sense Amplifier VOS
∆VFB
= FB∆V = 80mV– FB∆V = 0mV
200kΩ
1.0V
12VFigure 4. Positioning Voltage
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified all other
voltages re referenced to GND.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
VID4
VID3
VID2
VID1
VID0
VID5
FBRTN
COMP
PWRGD
DELAY
RAMPADJ
VCC
PWM1
PWM2
PWM3
PWM4
SW1
SW2
SW3
SW4
GND
CSCOMP
CSSUM
CSREF
ILIMIT04835-0-002
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS
MAS
CLOCK FRE
NCY
(MHz)
RT VALUE (kΩ)5010015020025030004835-0-003
Figure 6. Master Clock Frequency vs. RT
0.511.522.533.54
CURRE
NT (mA)
OSCILLATOR FREQUENCY (MHz)04835-0-004
Figure 7. Supply Current vs. Oscillator Frequency
THEORY OF OPERATION The ADP3188 combines a mulitmode, fixed frequency PWM
control with mulitphase logic outputs for use in 2-, 3- and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC is designed to interface with the Intel
6-bit VRD/VRM 10 and 10.1 compatible CPUs. Multiphase
operation is important for producing the high currents and low
voltages demanded by today’s microprocessors. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system such as the
inductors and MOSFETs.
The multimode control of the ADP3188 ensures a stable, high
performance topology for Balancing currents and thermals between phases High speed response at the lowest possible switching
frequency and output decoupling Minimizing thermal switching losses due to lower
frequency operation Tight load line regulation and accuracy High current output for up to 4-phase operation Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component
selection Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3188 operates as
a 4-phase PWM controller. Grounding the PWM4 pin programs
3-phase operation, and grounding the PWM3 and PWM4 pins
programs 2-phase operation.
When the ADP3188 is enabled, the controller outputs a voltage
on PWM3 and PWM4, which is approximately 675 mV. An
internal comparator checks each pin’s voltage versus a threshold
of 300 mV. If the pin is grounded, it is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation. PWM1 and PWM2
are disabled during the phase detection interval, which occurs
during the first two clock cycles of the internal oscillator. After
this time, if the PWM output is not grounded, the 5 kΩ
resistance is removed. and it switches between 0 V and 5 V. If
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
MASTER CLOCK FREQUENCY The clock frequency of the ADP3188 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are grounded,
then divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3188 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifier. This
maintains a worst-case specification of ±9.5 mV differential
sensing error over its full operating output voltage and tempera-
ture range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micro-
processor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal
current of 100 µA to allow accurate remote sensing. The internal
error amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
OUTPUT CURRENT SENSING The ADP3188 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system: Output inductor DCR sensing without a thermistor for
lowest cost Output inductor DCR sensing with a thermistor for
improved accuracy with tracking of inductor temperature Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current limit comparator.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. Also, the sensing
gain is determined by external resistors so that it can be made
extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output current
at the CSCOMP pin can be scaled to equal the droop impedance
of the regulator times the output current. This droop voltage is
then used to set the input control voltage to the system. The
droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifier where the output voltage
should be. This differs from previous implementations and allows
enhanced feed-forward response.
CURRENT CONTROL MODE AND
THERMAL BALANCE The ADP3188 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for positioning
described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control for changes in the supply. A
resistor connected from the power input voltage to the RAMPADJ
pin determines the slope of the internal PWM ramp. Detailed
information about programming the ramp is given in the
Application Information section.
External resistors can be placed in series with individual phases
to create, if desired, an intentional current imbalance such as
when one phase may have better cooling and can support higher
currents. Resistors RSW1 through RSW4 (see the typical application
circuit in Figure 10) can be used for adjusting thermal balance.
It is best to have the ability to add these resistors during the initial
design, so make sure that placeholders are provided in the layout.
To increase the current in any given phase, make RSW for that
phase larger (make RSW = 0 for the hottest phase and do not
change during balancing). Increasing RSW to only 500 Ω makes a
substantial increase in phase current. Increase each RSW value by
small amounts to achieve balance, starting with the coolest
phase first.
VOLTAGE CONTROL MODE A high gain bandwidth voltage mode error amplifier is used for
the voltage mode control loop. The control input voltage to the
positive input is set via the VID logic according to the voltages
listed in Table 4. This voltage is also offset by the droop voltage
for active positioning of the output voltage as a function of
current, commonly known as active voltage positioning. The
output of the amplifier is the COMP pin, which sets the termi-
nation voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor (RB) and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated
into the feedback network between FB and COMP.
SOFT START The power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch off
time as explained in the following section. In UVLO or when
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged with an internal 20 µA current source. The
output voltage follows the ramping voltage on the DELAY pin,
limiting the inrush current. The soft-start time depends on the
value of VID DAC and CDLY, with a secondary effect from RDLY.
Refer to the Application Information section for detailed infor-
mation on setting CDLY.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another soft-
start cycle. Figure 8 shows a typical soft-start sequence for the
ADP3188.
Figure 8. Typical Start-Up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION The ADP3188 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to give a current limit threshold of 10.4 mV/µA. If the
difference in voltage between CSREF and CSCOMP rises above
the current limit threshold, the internal current limit amplifier
controls the internal COMP voltage to maintain the average
output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V. The
Application Information section discusses the selection of CDLY
and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft-
start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3188, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft-start time because the current through it adds to the
internal 20 µA current source.
During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases
if one or more phases stops functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
Figure 9. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
DYNAMIC VID The ADP3188 has the ability to dynamically change the VID
input while the controller is running. This allows the output
voltage to change while the supply is running and supplying
current to the load. This is commonly referred to as VID on-
the-fly (OTF). A VID OTF can occur under either light or heavy
load conditions. The processor signals the controller by changing
the VID inputs in multiple steps from the start code to the finish
code. This change can be positive or negative.
When a VID input changes state, the ADP3188 detects the
change and ignores the DAC inputs for a minimum of 400 ns.
This time prevents a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD and CROWBAR blanking functions for a
minimum of 100 µs to prevent a false PWRGD or CROWBAR
event. Each VID change resets the internal timer.
Table 4. VID Codes for the ADP3188
POWER GOOD MONITORING The power good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified in the
specifications above based on the VID voltage setting. PWRGD
goes low if the output voltage is outside of this specified range,
if all of the VID DAC inputs are high, or whenever the EN pin is
pulled low. PWRGD is blanked during a VID OTF event for a
period of 250 µs to prevent false signals during the time the
output is changing.
The PWRGD circuitry also incorporates an initial turn-on delay
time based on the DELAY ramp. The PWRGD pin is held low
until the DELAY pin reaches 2.6 V. The time between when the
PWRGD undervoltage threshold is reached and when the
DELAY pin reaches 2.6 V provides the turn-on delay time. This
time is incorporated into the soft-start ramp. To ensure a 1 ms
delay time on PWRGD, the soft-start ramp must also be >1 ms.
Refer to the Application Information section for detailed
information on setting CDLY.
OUTPUT CROWBAR As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 550 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
current-limits the input supply or blows its fuse, protecting the
microprocessor from being destroyed.
OUTPUT ENABLE AND UVLO For the ADP3188 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and the
EN pin must be higher than its logic threshold. If UVLO is less
than the threshold or the EN pin is a logic low, the ADP3188 is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. The ILIMIT being
grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the
discharge of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated during output due to the high current
discharge of the output capacitors through the inductors.
FROM CPU
CC(
0.8375V
– 1.6V
95A TDC, 119A PKV
CC(
) RTN
370nH
2700
F/16V/3.3 A
15nF
2.2009
