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ADP3182JRQZ-REEL
Adjustable Output 1-/2-/3-Phase Synchronous Buck Controller
Adjustable Output 1-/2-/3-Phase
Synchronous Buck Controller
Rev. 0
FEATURES
Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per
phase
±2% worst-case differential sensing error over temperature
Externally adjustable 0.8 V to >5 V output from a 12 V supply
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar functions
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Auxiliary supplies
DDR memory supplies
Point-of-load modules
GENERAL DESCRIPTION The ADP3182 is a highly efficient multiphase, synchronous,
buck-switching regulator controller optimized for converting a
12 V main supply into a high current, low voltage supply for use
in point-of-load (POL) applications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 1-, 2-, or 3-phase operation, allowing
for the construction of up to three complementary buck-
switching stages. The ADP3182 also provides accurate and
reliable short-circuit protection and adjustable current limiting.
ADP3182 is specified over the commercial temperature range of
0°C to +85°C and is available in a 20-lead QSOP package.
FUNCTIONAL BLOCK DIAGRAM VCC
GND6
DELAY7
ILIMIT10
PWRGD5
RAMPADJ
PWM2FB
PWM3
SW1
CSSUM
CSCOMP
SW2
SW3
CSREF
PWM1
FBRTN
COMP4
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Test Circuits.......................................................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Description..............................7
Typical Performance Characteristics.............................................8
Theory of Operation........................................................................9
Start-Up Sequence........................................................................9
Master Clock Frequency..............................................................9
Output Voltage Differential Sensing..........................................9
Output Current Sensing..............................................................9
Current Control Mode and Thermal Balance........................10
Voltage Control Mode................................................................10
Soft Start......................................................................................10
Current Limit, Short-Circuit, and Latch-off Protection.......10
Power Good Monitoring...........................................................11
Output Crowbar.........................................................................11
Output Enable and UVLO........................................................12
Applications.....................................................................................14
Setting the Clock Frequency.....................................................14
Soft Start and Current Limit Latch-Off Delay Time.............14
Inductor Selection......................................................................14
Output Current Sense................................................................15
Output Voltage............................................................................16
Power MOSFETs.........................................................................16
Ramp Resistor Selection............................................................17
Current Limit Setpoint..............................................................17
Feedback Loop Compensation Design....................................17
Input Capacitor Selection and Input Current di/dt...............18
Inductor DCR Temperature Correction.................................18
Layout and Component Placement.........................................19
Outline Dimensions.......................................................................20
Ordering Guide..........................................................................20
REVISION HISTORY
10/04—Revision 0: Initial Version
SPECIFICATIONS VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production.
TEST CIRCUITS
12V
39kΩ
1kΩ
0.8V Figure 2. Current Sense Amplifier VOS
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTION
VCC
FBRTN
COMP
PWRGD
DELAY
RAMPADJ
ILIMIT
PWM1
PWM2
PWM3
SW1
SW2
SW3
GND
CSCOMP
CSSUM
CSREF04938-003
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions TYPICAL PERFORMANCE CHARACTERISTICS
MAS
CLOCK FRE
NCY
(MHz)
RT VALUE (kΩ)2502001501005030004938-004
Figure 4. Master Clock Frequency vs. RT
CURRE
NT (mA)
OSCILLATOR FREQUENCY (MHz)2.52.01.51.00.53.004938-005
Figure 5. Supply Current vs. Oscillator Frequency
THEORY OF OPERATION The ADP3182 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 1-, 2-, and
3-phase, synchronous, buck, point-of-load supply power
converters. Multiphase operation is important for producing the
high currents and low voltages demanded by auxiliary supplies
in desktop computers, workstations, and servers. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system, such as the
inductors and MOSFETs.
The multimode control of the ADP3182 ensures a stable, high
performance topology for Balancing currents and thermals between phases High speed response at the lowest possible switching
frequency and output decoupling Minimizing thermal switching losses due to lower
frequency operation Tight regulation and accuracy Reduced output ripple due to multiphase cancellation PC board layout noise immunity Ease of use and design due to independent component
selection Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3182 operates
as a 3-phase PWM controller. Grounding the PWM3 pin
programs 1/2-phase operation.
When the ADP3182 is enabled, the controller outputs a voltage
on PWM3 that is approximately 675 mV. An internal comparator
checks the pin’s voltage vs. a threshold of 300 mV. If the pin is
grounded, it is below the threshold and the phase is disabled.
The output resistance of the PWM pin is approximately 5 kΩ
during this detection time. Any external pull-down resistance
connected to the PWM pin should be more than 25 kΩ to
ensure proper operation. PWM1 and PWM2 are disabled
during the phase detection interval, which occurs during the
first two clock cycles of the internal oscillator. After this time, if
the PWM output is not grounded, the 5 kΩ resistance is
removed, and the PWM output switches between 0 V and 5 V. If
the PWM output is grounded, it remains off.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
MASTER CLOCK FREQUENCY The clock frequency of the ADP3182 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 4. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM3 is grounded, then divide the master clock by 2 for the
frequency of the remaining two phases.
It is important to note that if only one phase is used, the clock
will switch as if two phases were operating. This means that the
oscillator frequency must be set at twice the expected value to
program the desired PWM frequency.
OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3182 uses a differential-sensing, low offset voltage error
amplifier. This maintains a worst-case specification of ±2%
differential-sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the local bypass
capacitor for the load. FBRTN should be connected directly to
the remote sense ground point. The internal precision reference
is referenced to FBRTN, which has a minimal current of 100 µA
to allow accurate remote sensing. The internal error amplifier
compares the output of the reference to the FB pin to regulate
the output voltage.
OUTPUT CURRENT SENSING The ADP3182 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for current limit
detection. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the low-
side MOSFET. This amplifier can be configured several ways
depending on the objectives of the system: Output inductor DCR sensing without a thermistor for
lowest cost Output inductor DCR sensing with a thermistor for
improved accuracy for tracking inductor temperature Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
gain of the amplifier is programmable by adjusting the feedback
resistor. The current information is then given as the difference
of CSREF − CSCOMP. This difference in signal is used as a
differential input for the current limit comparator.
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is determined by external resistors so that the gain
can be made extremely accurate.
CURRENT CONTROL MODE AND
THERMAL BALANCE The ADP3182 has individual inputs for each phase that are used
for monitoring the current in each phase. This information is
combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the current
limit described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control to compensate for changes in
the supply voltage. A resistor connected from the power input
voltage to the RAMPADJ pin determines the slope of the
internal PWM ramp. External resistors can be placed in series
with individual phases to create, if desired, an intentional
current imbalance such as when one phase may have better
cooling and can support higher currents. Resistors RSW1 through
RSW3 (see the typical application circuit in Figure 9) can be used
for adjusting thermal balance. Add placeholders for these
resistors during the initial layout so that adjustments can be made
after completing thermal characterization of the design.
To increase the current in any given phase, increase RSW for that
phase (set RSW = 0 for the hottest phase and do not change it
during balancing). Increasing RSW to only 500 Ω substantially
increases the phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase.
VOLTAGE CONTROL MODE A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is derived from the internal 800 mV reference.
The output of the amplifier is the COMP pin, which sets the
termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the center point of a resistor
divider from the output sense location. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
SOFT START The power-on, ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-
off time as explained in the following section. In UVLO or
when EN is logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush. The soft start time depends on
the value of CDLY, with a secondary effect from RDLY.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to prepare for another soft
start cycle. Figure 6 shows a typical soft start sequence for the
ADP3182.
04938-006
Figure 6. Typical Start-Up Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: PWRGD, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION The ADP3182 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to produce a current limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current limit threshold, the internal current limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.
