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ADP3181JRUZ-REEL ,5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck ControllerFEATURES FUNCTIONAL BLOCK DIAGRAM VCC RAMPADJ RTSelectable 2-, 3- or 4-phase operation at up to 1 M ..
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ADP3188JRUZ-REEL ,6-Bit Programmable 2-/3-/4-Phase Synchronous Buck ControllerSpecifications.... 3 Inductor Selection ....... 15 Test Circuits...... 5 Designing an Inductor 16 A ..
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ADP3181-ADP3181JRUZ-REEL
5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller
5-Bit or 6-Bit Programmable 2-,3-,4-Phase
Synchronous Buck Controller
Rev. 0
FEATURES
Selectable 2-, 3- or 4-phase operation at up to 1 MHz per
phase
±14.5 mV worst-case mV differential sensing error over
temperature
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar blanking supports on-the-fly
VID code changes
Digitally programmable output can be switched between
VRM 9 (5-bit) and VRD 10 (6-bit) VID codes
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Desktop PC power supplies for:
Next-generation Intel® processors
VRM modules
GENERAL DESCRIPTION The ADP3181 is a highly efficient multiphase synchronous
buck-switching regulator controller optimized for converting
a 12 V main supply into the core supply voltage required by
high performance Intel processors. It uses an internal 6-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage. The
CPUID input selects whether the DAC codes match the
VRM 9 or VRD 10 specifications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can
be programmed to provide 2-, 3-, or 4-phase operation,
allowing for the construction of up to four complementary
buck-switching stages.
The ADP3181 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a
system transient. The ADP3181 provides accurate and reliable
short-circuit protection, adjustable current limiting, and a
delayed power good output that accommodates on-the-fly
output voltage changes requested by the CPU.
The device is specified over the commercial temperature range
of 0°C to +85°C and is available in a 28-lead TSSOP package.
FUNCTIONAL BLOCK DIAGRAM 34576
GND
DELAY
ILIMIT
PWRGDRAMPADJ
PWM2
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
VID4VID3VID2VID1VID0FBRTNCPUID
COMP04796-0-001
Figure 1.
TABLE OF CONTENTSSpecifications.....................................................................................3
Test Circuits.......................................................................................5
Absolute Maximum Ratings............................................................6
Pin Configuration and Function Descriptions.............................7
Typical Performance Characteristics.............................................8
Theory of Operation........................................................................9
Start-up Sequence.........................................................................9
Master Clock Frequency............................................................10
Output Voltage Differential Sensing........................................10
Output Current Sensing............................................................11
Active Impedance Control Mode.............................................11
Current Control Mode and Thermal Balance.......................11
Voltage Control Mode................................................................11
Soft Start......................................................................................12
Current Limit, Short-Circuit, and Latch-Off Protection.......12
Dynamic VID..............................................................................13
Power Good Monitoring...........................................................13
Output Crowbar.........................................................................13
Output Enable and UVLO........................................................13
Application Information................................................................15
Setting the Clock Frequency.....................................................15
Soft-Start and Current-Limit Latch-Off Delay Times...........15
Inductor Selection......................................................................15
Designing an Inductor...............................................................16
Output Droop Resistance..........................................................16
Inductor DCR Temperature Correction.................................17
Output Offset..............................................................................17
Cout Selection...............................................................................17
Power MOSFETS........................................................................18
Ramp Resistor Selection............................................................19
Current Limit Setpoint..............................................................20
Feedback Loop Compensation Design....................................20
CIN Selection and Input Current di/dt Reduction..................21
Building a Switchable VR9/VR10 Design...............................22
Layout and Component Placement.............................................23
General Recommendations.......................................................23
Outline Dimensions.......................................................................24
Ordering Guide..........................................................................24
REVISION HISTORY
5/04—Revision 0: Initial Version
SPECIFICATIONSVCC = 12 V, FBRTN = GND, TA = 0°C to +85°C, unless otherwise noted.1
Table 1.
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC). Guaranteed by design or bench characterization, not tested in production.
TEST CIRCUITS
12V
100nF
ADP3181
100nF04796-0-004
Figure 2. Closed-Loop Output Voltage Accuracy
39kΩ
1kΩ
1.0V
12V
Figure 3. Current Sense Amplifier VOS
200kΩ
1.0V
∆VFB = FB∆V = 80mV– FB∆V = 0mV
Figure 4. Positioning Voltage
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Absolute maximum ratings apply individually only, not in
combination. Unless otherwise specified all other voltages are
referenced to GND.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VID4VCC
VID3PWM1
VID2PWM2
VID1PWM3
VID0PWM4
CPUIDSW1
FBRTNSW2SW3
COMPSW4
PWRGDGNDCSCOMP
DELAYCSSUMCSREF
RAMPADJILIMIT
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
TYPICAL PERFORMANCE CHARACTERISTICS 050100150200250300RT VALUE (kΩ)
MAS
CLOCK FRE
NCY
(MHz)
Figure 6. Master Clock Frequency vs. RT
4.604.03.53.02.52.01.51.00.5OSCILLATOR FREQUENCY (MHz)
CURRE
NT (mA)
Figure 7. Supply Current vs. Oscillator Frequency
THEORY OF OPERATION The ADP3181 combines a multimode, fixed-frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal VID DAC can be used in the Intel 5-bit VRM 9 or
6-bit VRD/VRM 10 designs, depending on the setting of the
CPUID pin. Multiphase operation is important for producing
the high currents and low voltages demanded by today’s micro-
processors. Handling the high currents in a single-phase
converter places high thermal demands on the components
in the system such as the inductors and MOSFETs. The
multimode control of the ADP3181 ensures a stable, high
performance topology for Balancing currents and thermals between phases. High speed response at the lowest possible switching
frequency and output decoupling. Minimizing thermal switching losses due to lower
frequency operation. Tight load line regulation and accuracy. High current output from 4-phase operational design. Reduced output ripple due to multiphase cancellation. PC board layout noise immunity. Ease of use and design due to independent component
selection. Flexibility in operation for tailoring design to low cost or
high performance.
START-UP SEQUENCE Two functions are set during the start-up sequence: the number
of active phases and the VID DAC configuration. The number
of operational phases and their phase relationship is determined
by internal circuitry that monitors the PWM outputs. Normally,
the ADP3181 operates as a 4-phase PWM controller. Grounding
the PWM4 pin programs 3-phase operation, and grounding the
PWM3 and PWM4 pins programs 2-phase operation.
When the ADP3181 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 675 mV. An
internal comparator checks each pin’s voltage versus a threshold
of 300 mV. If the pin is grounded, it is below the threshold and
the phase is disabled. The output resistance of the PWM pin is
approximately 5 kΩ during this detection time. Any external
pull-down resistance connected to the PWM pin should not be
less than 25 kΩ to ensure proper operation.
PWM1 and PWM2 are disabled during the phase detection
interval, which occurs during the first two clock cycles of the
internal oscillator. After this time, if the PWM output was not
grounded, the 5 kΩ resistance is removed and it switches
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
The VID DAC configuration is determined by the voltage at the
CPUID pin. If this pin is pulled up to > 4.5 V, the VID DAC
operates with five inputs and generates the VR 9 output voltage
range as shown in Table 4. If CPUID is < 4 V, the VID DAC
treats CPUID as the VID5 input of VR 10, and operates as a 6-
bit DAC using the output voltage range given in Table 5.
Table 4. VR 9 VID Codes for the ADP3181, CPUID > 4.25
Table 5. VR 10 VID Codes for the ADP3181, CPUID Used as a VID5 Input
MASTER CLOCK FREQUENCYThe clock frequency of the ADP3181 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 6. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM4 is grounded, then divide the master clock by 3 for the
frequency of the remaining phases. If PWM3 and 4 are
grounded, divide by 2. If all phases are in use, divide by 4.
OUTPUT VOLTAGE DIFFERENTIAL SENSING The ADP3181 combines differential sensing with a high
accuracy VID DAC and reference and a low offset error
amplifier to maintain a worst-case specification of ±14.5 mV
differential sensing error over its full operating output voltage
and temperature ranges. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and
precision reference are referenced to FBRTN, which has a
minimal current of 100 µA to allow accurate remote sensing.
The internal error amplifier compares the output of the DAC to
the FB pin to regulate the output voltage.
OUTPUT CURRENT SENSING The ADP3181 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
This amplifier can be configured several ways depending on the
objectives of the system: Output inductor ESR sensing without a thermistor for
lowest cost. Output inductor ESR sensing with a thermistor for
improved accuracy with tracking of inductor temperature. Sense resistors for highest accuracy measurements.
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
gain of the amplifier is programmable by adjusting the feedback
resistor to set the load line required by the microprocessor. The
current information is then given as the difference of CSREF –
CSCOMP. This difference signal is used internally to offset the
VID DAC for voltage positioning and as a differential input for
the current limit comparator.
To provide the best accuracy for the sensing of current, the CSA
has been designed to have a low offset input voltage. Also, the
sensing gain is determined by external resistors so that it can be
made extremely accurate.
ACTIVE IMPEDANCE CONTROL MODE For controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output
current at the CSCOMP pin can be scaled to equal the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the
system. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.
CURRENT CONTROL MODE AND
THERMAL BALANCE The ADP3181 has individual inputs for each phase, which are
used for monitoring the current in each phase. This information
is combined with an internal ramp to create a current balancing
feedback system that has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the positioning
described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It is also monitors the
supply voltage for feed-forward control for changes in the
supply. A resistor connected from the power input voltage to
the RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.
If desired, external resistors can be placed in series with
individual phases to create an intentional current imbalance if
desired, such as when one phase may have better cooling and
can support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 10) can be used for
adjusting thermal balance. It is best to have the ability to add
these resistors during the initial design, so make sure
placeholders are provided in the layout.
To increase the current in any phase, make RSW for that phase
larger (make RSW = 0 for the hottest phase; do not change during
balancing). Increasing RSW to only 500 Ω makes a substantial
increase in phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase first.
VOLTAGE CONTROL MODE A high gain bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID logic. This voltage is also offset
by the droop voltage for active positioning of the output voltage
as a function of current, commonly known as active voltage
positioning. The output of the amplifier is the COMP pin,
which sets the termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage is negative with respect to
the VID DAC. The main loop compensation is incorporated in
the feedback network between FB and COMP.
SOFT STARTThe power-on ramp-up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current limit
latch off time as explained in the following section. In UVLO or
when EN is a logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is a logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the in-rush current. The soft-start time
depends on the value of VID DAC and CDLY, with a secondary
effect from RDLY. Refer to the Application Information section
for detailed information on setting CDLY.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to be ready for another
soft-start cycle. Figure 8 shows the typical start-up waveforms
for the ADP3181.
Figure 8. Typical Start-up Waveforms
Channel 1: PWRGD, Channel 2: CSREF,
Channel 3: DELAY, Channel 4: COMP
CURRENT LIMIT, SHORT-CIRCUIT, AND LATCH-
OFF PROTECTION The ADP3181 compares a programmable current-limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the
ILIMIT pin to ground. During normal operation, the voltage on
ILIMIT is 3 V. The current through the external resistor is inter-
nally scaled to give a current-limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current-limit threshold, the internal current-limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the
DELAY voltage and shuts off the controller when the voltage
drops below 1.8 V. The current-limit latch-off delay time is thus
set by the RC time constant discharging from 3 V to 1.8 V. The
Application Information section discusses the selection of CDLY
and RDLY.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller returns to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft-
start cycle is initiated.
The latch-off function can be reset either by removing and
reapplying VCC to the ADP3181, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the delay capacitor from discharging so the
1.8 V threshold is never reached. The resistor has an impact on
the soft-start time because the current through it adds to the
internal 20 µA current source.
Figure 9. Overcurrent Latch-off Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: COMP, Channel 4: Phase 1 Switch Node
During start-up when the output voltage is below 200 mV, a
secondary current limit is active because the voltage swing of
CSCOMP cannot go below ground. This secondary current
limit controls the internal COMP voltage to the PWM
comparators to 2 V. This limits the voltage drop across the low-
side MOSFETs through the current balance circuitry.
There is also an inherent per phase current limit that protects
individual phases if one or more phases stops functioning
because of a faulty component. This limit is based on the
maximum normal mode COMP voltage.
