ADP3168JRU-REEL ,6-Bit Programmable2 /3/4-Phase Synchronous Buck ControllerGENERAL DESCRIPTIONThe ADP3168 is a highly effi cient multiphase synchronous buck 23SW1switching reg ..
ADP3168JRU-REEL7 ,6-Bit Programmable2 /3/4-Phase Synchronous Buck ControllerFEATURES FUNCTIONAL BLOCK DIAGRAMSelectable 2-, 3-, or 4-Phase Operation at up to VCC RAMPADJ RT ..
ADP3168JRUZ-REEL ,6-Bit Programmable2 /3/4-Phase Synchronous Buck Controller6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller*ADP3168
ADP3170JRU ,VRM 8.5 Compatible Single Phase Core ControllerSPECIFICATIONS (VCC = 12 V, I = 150 A, T = 0C to 70C, unless otherwise noted.)REF AParameter Sym ..
ADP3170JRU-REEL ,VRM 8.5 Compatible Single Phase Core ControllerSPECIFICATIONS (VCC = 12 V, I = 150 A, T = 0C to 70C, unless otherwise noted.)REF AParameter Sym ..
ADP3178JR ,4-Bit Programmable Synchronous Buck Controllerspecifications for high- and have been designed to provide a high bandwidth load-performance proces ..
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ADP3168JRU-REEL-ADP3168JRU-REEL7-ADP3168JRUZ-REEL
6-Bit Programmable2 /3/4-Phase Synchronous Buck Controller
6-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller*Patent Pending
FEATURES
Selectable 2-, 3-, or 4-Phase Operation at up to
1 MHz per Phase
±10 mV Worst-Case Differential Sensing Error over
Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-In Power Good/Crowbar Blanking Supports
On-the-Fly VID Code Changes
6-Bit Digitally Programmable 0.8375 V to 1.6 V Output
Programmable Short-Circuit Protection with
Programmable Latch-Off Delay
APPLICATIONS
Desktop PC Power Supplies for:
Next Generation Intel® Processors
VRM Modules
FUNCTIONAL BLOCK DIAGRAM
PWM2
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
VID4VID3VID2VID1VID5VID0FBRTN
GND
DELAY
ILIMIT
PWRGD
COMP
VCCRTRAMPADJ
GENERAL DESCRIPTIONThe ADP3168 is a highly effi cient multiphase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. It uses an internal 6-bit DAC to read
a voltage identifi cation (VID) code directly from the processor,
which is used to set the output voltage between 0.8375 V and
1.6 V, and uses a multimode PWM architecture to drive the
logic-level outputs at a programmable switching frequency that
can be optimized for VR size and effi ciency. The phase relation-
ship of the output signals can be programmed to provide 2-, 3-,
or 4-phase operation, allowing for the construction of up to four
complementary buck switching stages.
The ADP3168 also includes programmable no-load offset and
slope functions to adjust the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3168 also provides accurate and reliable short-
circuit protection, adjustable current limiting, and a delayed Power
Good output that accommodates on-the-fl y output voltage
changes requested by the CPU.
ADP3168 is specifi ed over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
REV. A
ADP3168–SPECIFICATIONS1
(VCC = 12 V, FBRTN = GND, TA = 0�C to 85�C, unless otherwise noted.)NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
ADP3168Specifi cations subject to change without notice.
ADP3168
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +15 V
FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VID0–VID5, EN, DELAY, ILIMIT, CSCOMP, RT,
PWM1–PWM4, COMP . . . . . . . . . . . . . . . .–0.3 V to +5.5 V
SW1–SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–5 V to +25 V
All Other Inputs and Outputs . . . . . . . . .–0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . . 0°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . .125°C
Storage Temperature Range . . . . . . . . . . . . . .–65°C to +150°C
Junction to Air Thermal Resistance (�JA) . . . . . . . . . . .100°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . . .300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specifi cation is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specifi ed, all other voltages
are referenced to GND.
ORDERING GUIDE
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily ac cu mu late
on the human body and test equipment and can discharge without detection. Although the ADP3168
features proprietary ESD pro tec tion circuitry, permanent damage may occur on devices subjected to high
energy electrostatic discharges. Therefore, proper ESD pre cau tions are rec om mend ed to avoid per for mance
deg ra da tion or loss of functionality.
PIN FUNCTION DESCRIPTIONS8FB
9COMP
24–27
ADP3168–Typical Performance Characteristics
MASTER CLOCK FREQ
UENCY – MHz
RT VALUE – k�50 100 150 200 250 300
SEE EQUATION 1 FOR FREQUENCIES NOT ON THIS GRAPHTPC 1. Master Clock Frequency vs. RT
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SUPPL
Y CURRENT – mA
MASTER CLOCK FREQUENCY – MHzTPC 2. Supply Current vs. Master Clock Frequency
TEST CIRCUITSTest Circuit 1. Current Sense Amplifi er VOS
Test Circuit 3. Closed-Loop Output Voltage Accuracy
X = Don’t Care
Table I. Output Voltage vs. VID Code
THEORY OF OPERATIONThe ADP3168 combines a multimode, fi xed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and
4-phase synchronous buck CPU core supply power converters.
The internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifi cations. Multiphase operation is important for produc-
ing the high currents and low voltages demanded by today’s
microprocessors. Handling the high currents in a single-phase
converter would place high thermal demands on system compo-
nents such as inductors and MOSFETs.
The multimode control of the ADP3168 ensures a stable, high
performance topology for
∑ Balancing currents and thermals between phases
∑ High speed response at the lowest possible switching frequen-
cy and output decoupling
∑ Minimizing thermal switching losses due to lower frequency
operation
∑ Tight load line regulation and accuracy∑ Ease of use and design due to independent component
selection∑ Flexibility in operation for tailoring design to low cost or
high performance
Number of PhasesThe number of operational phases and their phase relationship
is determined by the internal circuitry that monitors the PWM
outputs. Normally, the ADP3168 operates as a 4-phase PWM
controller. Grounding the PWM4 pin programs 3-phase operation;
grounding the PWM3 and PWM4 pins programs 2-phase operation.
When the ADP3168 is enabled, the controller outputs a voltage
on PWM3 and PWM4 of approximately 550 mV. An internal
comparator checks each pin’s voltage versus a threshold of
400 mV. If the pin is grounded, the voltage will be below the
threshold and the phase will be disabled. The output resistance
of the PWM pin is approximately 5 kW during this detection
time. Any external pull-down resistance connected to the
PWM pin should be at least 25 kW to ensure proper operation.
The phase detection is made during the fi rst two clock cycles of
ADP3168The PWM outputs become logic-level devices once normal opera-
tion starts. The detection is normal and is intended for driving
external gate drivers such as the ADP3418. Since each phase
is monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at any
given time for overlapping phases.
Master Clock FrequencyThe clock frequency of the ADP3168 is set with an external
resistor connected from the RT pin to ground. The frequency fol-
lows the graph in TPC 1. To determine the frequency per phase,
the clock is divided by the number of phases in use. If PWM4 is
grounded, divide the master clock by 3 for the frequency of the
remaining phases. If PWM3 and PWM4 are grounded, divide by 2.
If all phases are in use, divide by 4.
Output Voltage Differential SensingThe ADP3168 combines differential sensing with a high accuracy
VID DAC and reference and a low offset error amplifi er to main-
tain a worst-case specifi cation of ±10 mV differential sensing
error with a VID input of 1.6000 V over its full operating output
voltage and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the remote sense pin of
the microprocessor. FBRTN should be connected directly to the
remote sense ground point. The internal VID DAC and precision
reference are referenced to FBRTN, which has a minimal current
of 90 µA to allow accurate remote sensing. The internal error
amplifi er compares the output of the DAC to the FB pin to regu-
late the output voltage.
Output Current SensingThe ADP3168 provides a dedicated current sense amplifi er (CSA)
to monitor the total output current for proper voltage positioning
versus load current and for current limit detection. Sensing the
load current at the output gives the total average current being
delivered to the load, which is an inherently more accurate method
than peak current detection or sampling the current across a sense
element such as the low-side MOSFET. This amplifi er can be con- gured several ways, depending on the objectives of the system:∑ Output inductor ESR sensing without thermistor for lowest cost∑ Output inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperature∑ Sense resistors for most accurate measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifi er are summed together through resistors from the sensing
element (such as the switch node side of the output inductors)
to the inverting input, CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifi er, and a lter capacitor is placed in parallel with this resistor. The gain of
the amplifi er is programmable by adjusting the feedback resistor
to set the load line required by the microprocessor. The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset the VID DAC
for voltage positioning and as a differential input for the current
limit comparator.
To provide the best accuracy for the sensing of current, the CSA
Active Impedance Control ModeFor controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur-
rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the system.
The droop voltage is subtracted from the DAC reference input
voltage directly to tell the error amplifi er where the output volt-
age should be. This differs from previous implementations and
allows enhanced feed-forward response.
Current Control Mode and Thermal BalanceThe ADP3168 has individual inputs that are used for monitoring
the current in each phase. This information is combined with an
internal ramp to create a current balancing feedback system that
has been optimized for initial current balance accuracy and dynamic
thermal balancing during operation. This current balance infor-
mation is independent of the average output current information
used for positioning described previously.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply volt-
age for feed-forward control for changes in the supply. A resistor
connected from the power input voltage to the RAMPADJ pin
determines the slope of the internal PWM ramp. Detailed infor-
mation about programming the ramp is given in the Application
Information section.
External resistors can be placed in series with individual phases
to create an intentional current imbalance so that one phase may
have better cooling and can support higher currents, for example.
Resistors RSW1 through RSW4 (see the typical application circuit in
Figure 4) can be used for adjusting thermal balance. It is best to
have the ability to add these resistors during the initial design, so
make sure placeholders are provided in the layout.
To increase the current in any given phase, make RSW for that
phase larger. (Make RSW = 0 for the hottest phase and do not
change during balancing.) Increasing RSW to only 500 W will make
a substantial increase in phase current. Increase each RSW value
by small amounts to achieve balance, starting with the coolest
phase fi rst.
Voltage Control ModeA high gain-bandwidth voltage mode error amplifi er is used for
the voltage-mode control loop. The control input voltage to the
positive input is set via the VID 6-bit logic code, according to the
voltages listed in Table I. This voltage is also offset by the droop
voltage for active positioning of the output voltage as a function
of current, commonly known as active voltage positioning. The
output of the amplifi er is the COMP pin, which sets the termina-
tion voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor RB and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin fl owing
through RB is used for setting the no-load offset voltage from the
VID voltage. The no-load voltage will be negative with respect to
the VID DAC. The main loop compensation is incorporated into
the feedback network between FB and COMP.
Soft-StartThe power-on ramp-up time of the output voltage is set with
a capacitor and a resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current limit
latch-off time as explained in the following section. In UVLO
or when EN is a logic low, the DELAY pin is held at ground.
After the UVLO threshold is reached and EN is a logic high,
the DELAY capacitor is charged up with an internal 20 µA cur-
rent source. The output voltage follows the ramping voltage on
the DELAY pin, limiting the inrush current. The soft-start time
depends on the values of VID DAC and CDLY, with a secondary
effect from RDLY. Refer to the Application Information section for
detailed information on setting CDLY.
When the PWRGD threshold is reached, the soft-start cycle is
stopped and the DELAY pin is pulled up to 3 V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or VCC drops below UVLO, the DELAY capacitor is
reset to ground to be ready for another soft-start cycle. Figure 1
shows a typical start-up sequence for the ADP3168.
Figure 1. Start-Up Waveforms, Circuit of Figure 5.
Channel 1—PWRGD, Channel 2—VOUT, Channel 3—
High-Side MOSFET VGS, Channel 4—Low-Side
MOSFET VGS
Current Limit, Short Circuit, and Latch-Off ProtectionThe ADP3168 compares a programmable current limit set point
to the voltage from the output of the current sense amplifi er. The
level of current limit is set with the resistor from the ILIMIT pin
to ground. During normal operation, the voltage on ILIMIT is 3 V.
The current through the external resistor is internally scaled to
give a current limit threshold of 10.4 mV/µA. If the difference in
voltage between CSREF and CSCOMP rises above the current
limit threshold, the internal current limit amplifi er will control the
internal COMP voltage to maintain the average output current at
the limit.
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops below
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller will return to normal opera-
tion. The recovery characteristic depends on the state of PWRGD.
If the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has caused
the output voltage to drop below the PWRGD threshold, a soft-
start cycle is initiated.
The latch-off function can be reset either by removing and reap-
plying VCC to the ADP3168 or by pulling the EN pin low for
a short time. To disable the short circuit latch-off function, the
external resistor to ground should be left open, and a high value
(>1 MW) resistor should be connected from DELAY to VCC.
This prevents the DELAY capacitor from discharging, so the
1.8 V threshold is never reached. The resistor will have an impact
on the soft-start time because the current through it will add to
the internal 20 µA current source.
Figure 2. Overcurrent Latch-Off Waveforms, Circuit of
Figure 4. Channel 1—PWRGD, Channel 2—VOUT,
Channel 3—CSCOMP Pin of ADP3168, Channel 4—
High-Side MOSFET VGS
During startup, when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This sec-
ondary current limit controls the internal COMP voltage to the
PWM comparators to 2 V. This will limit the voltage drop across
the low-side MOSFETs through the current balance circuitry.
There is also an inherent per-phase current limit that will protect
individual phases in the case where one or more phases may stop
functioning because of a faulty component. This limit is based on
the maximum normal mode COMP voltage.
Dynamic VIDThe ADP3168 incorporates the ability to dynamically change the
VID input while the controller is running. This allows the output
voltage to change while the supply is running and supplying cur-
rent to the load. This is commonly referred to as VID on-the-fl y
(OTF). A VID OTF can occur under either light load or heavy
load conditions. The processor signals the controller by changing
ADP3168When a VID input changes state, the ADP3168 detects the change
and ignores the DAC inputs for a minimum of 400 ns. This pre-
vents a false code due to logic skew while the six VID inputs are
changing. Additionally, the fi rst VID change initiates the PWRGD
and CROWBAR blanking functions for a minimum of 250 µs
to prevent a false PWRGD or CROWBAR event. Each VID
change will reset the internal timer. Figure 3 shows VID on-the-fl y
performance when the output voltage is stepping up and the output
current is switching between minimum and maximum values,
which is the worst-case situation.
Figure 3. VID On-the-Fly Waveforms, Circuit of Figure 5.
VID Change = 5 mV, 5 µs per Step, 50 Steps, IOUT Change =
5 A to 65 A
Power Good MonitoringThe Power Good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specifi ed in the Speci- cations table based on the VID voltage setting. PWRGD will go
low if the output voltage is outside of this specifi ed range. PWRGD
is blanked during a VID OTF event for a period of 250 µs to
prevent false signals during the time the output is changing.
Output CrowbarAs part of the protection for the load and output components of
the supply, the PWM outputs will be driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
Power Good threshold. This crowbar action will stop once the
output voltage has fallen below the release threshold of approxi-
mately 450 mV.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output overvolt-
age is due to a short of the high-side MOSFET, this action will
current limit the input supply or blow its fuse, protecting the
microprocessor from destruction.
Output Enable and UVLOThe input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher than its
logic threshold for the ADP3168 to begin switching. If UVLO is
less than the threshold or the EN pin is a logic low, the ADP3168
is disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers so that both DRVH and
DRVL are grounded. This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
the output capacitors through the inductors.
APPLICATION INFORMATIONThe design parameters for a typical Intel VRD 10 compliant
CPU application are as follows:
Input Voltage (VIN) = 12 V
VID Setting Voltage (VVID) = 1.500 V
Duty Cycle (D) = 0.125
Nominal Output Voltage at No Load (VONL) = 1.480 V
Nominal Output Voltage at 65 A Load (VOFL) = 1.3955 V
Static Output Voltage Drop Based on a 1.3 mW Load Line (RO) from No Load to Full Load
(VD) = VONL – VOFL = 1.480 V – 1.3955 V = 84.5 mV
Maximum Output Current (IO) = 65 A
Maximum Output Current Step (DIO) = 60 A
Number of Phases (n) = 3
Switching Frequency per Phase (fSW) = 267 kHz
Setting the Clock FrequencyThe ADP3168 uses a fi xed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 800 kHz sets
the switching frequency of each phase, fSW, to 267 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output fi lter components. TPC 1 shows that to
achieve an 800 kHz oscillator frequency, the correct value for RT
is 249 kW. Alternatively, the value for RT can be calculated using
(1)
where 5.83 pF and 1.5 MW are internal IC component values.
For good initial accuracy and frequency stability, a 1% resistor is
recommended.
