ADP3166JRU-REEL ,5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck ControllerGENERAL DESCRIPTIONILIMIT 15The ADP3166 is a highly efficient, multiphase, synchronous17 CSSUMCURRE ..
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ADP3166-ADP3166JRU-REEL
5-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller
REV.0
5-Bit Programmable 2-, 3-, 4-Phase
Synchronous Buck Controller*Patent pending
FEATURES
Selectable 2-, 3- or 4-Phase Operation at up to
1 MHz per Phase
Differential Sensing Error ±1% over Temperature
Logic-Level PWM Outputs for Interface to
External High Power Drivers
Active Current Balancing between All Output Phases
Built-in Power Good Blanking Supports On-the-Fly
VID Code Changes
5-Bit Digitally Programmable 0.8 V to 1.55 V Output
Short-Circuit Protection with Programmable
Latch-Off Delay
Overvoltage Protection Crowbar Logic Output
APPLICATIONS
Desktop PC Power Supplies
Next-Generation AMD Processors
VRM Modules
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
DELAY
ILIMIT
PWRGDRAMPADJ
PWM2
PWM3
PWM4
SW1
CSSUM
CSCOMP
SW2
SW3
SW4
CSREF
PWM1
VID4VID3VID2VID1VID0FBRTN
COMP
CROWBAR12345
GENERAL DESCRIPTIONThe ADP3166 is a highly efficient, multiphase, synchronous
buck switching regulator controller optimized for converting a
12 V main supply into the core supply voltage required by high
performance AMD processors. It uses an internal 5-bit DAC to
read a voltage identification (VID) code directly from the pro-
cessor, which is used to set the output voltage between 0.8 V
and 1.55 V. The ADP3166 also uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The phase relationship of the output signals can be
programmed to provide 2-, 3-, or 4-phase operation, allowing
for the construction of up to four complementary buck switch-
ing stages.
The ADP3166 includes programmable no-load offset and slope
functions to adjust the output voltage as a function of the load
current so that it is always optimally positioned for a system
transient. The ADP3166 also provides accurate and reliable
short-circuit protection, adjustable current limiting, and a delayed
power good output that accommodates on-the-fly output volt-
age changes requested by the CPU.
ADP3166 is specified over the commercial temperature range of
0°C to 85°C and is available in a 28-lead TSSOP package.
ADP3166–SPECIFICATIONS1VID INPUTS
CURRENT SENSE AMPLIFIER
CURRENT BALANCE CIRCUIT
(VCC = 12 V, FBRTN = GND, TA = 0�C to 85�C, unless otherwise noted.)
ADP3166NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).Guaranteed by design, not tested in production.
Specifications subject to change without notice.
POWER GOOD COMPARATOR
CROWBAR COMPARATOR
ADP3166
ABSOLUTE MAXIMUM RATINGS*VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +15 V
FBRTN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +0.3 V
VID0 to VID4, EN, DELAY, ILIMIT, CSCOMP, RT, COMP,
CROWBAR, PWM1 to PWM4 . . . . . . . . .–0.3 V to +5.5 V
SW1 to SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . .–5 V to +25 V
All Other Inputs and Outputs . . . . . . .–0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . 0°C to 85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . .125°C
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
�JA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100°C/W
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
SUPPL
Y CURRENT – mA
MASTER CLOCK FREQUENCY – MHzTPC 1. Supply Current vs. Master Clock Frequency
ORDERING GUIDELead Temperature (Soldering, 10 sec) . . . . . . . . . . . . .300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only. Functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
other voltages are referenced to GND.
MASTER CLOCK FREQ
UENCY – MHz
RT VALUE – kΩ
050100150200250300TPC 2. Master Clock Frequency vs. RT
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3166 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
Test Circuit 2. Positioning Amplifier VOS Test Circuit
80mVTest Circuit 3. Positioning Voltage Test Circuit
5-BIT CODETest Circuit 1. Closed-Loop Output Voltage Accuracy
ADP3166
PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
RU-28
THEORY OF OPERATIONThe ADP3166 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 2-, 3-, and 4-phase
synchronous buck CPU core supply power converters. The
internal 5-bit VID DAC conforms to AMD’s Hammer family
power specifications. Multiphase operation is important for
producing the high currents and low voltages demanded by
today’s microprocessors. Handling the high currents in a single-
phase converter would place high thermal demands on the
components in the system such as the inductors and MOSFETs.
The multimode control of the ADP3166 ensures a stable, high
performance topology forBalancing currents and thermals between phases.High speed response at the lowest possible switching frequency
and output decoupling.Minimizing thermal switching losses due to lower frequency
operation.Tight load line regulation and accuracy.High current output from having up to 4-phase operation.Reduced output ripple utilizing multiphase cancellation.Immunity to board layout.Ease of use and design due to independent component
selection.Flexibility in operation for tailoring design to low cost or
high performance.
Number of PhasesThe number of operational phases and their phase relationship
are determined by internal circuitry that monitors the PWM
outputs. Normally, the ADP3166 operates as a 4-phase PWM
controller. Grounding the PWM 4 pin programs 3-phase opera-
tion, and grounding the PWM3 and PWM4 pins programs
2-phase operation.
When the ADP3166 is enabled, the controller outputs a voltage
on PWM3 and PWM4 that is approximately 550mV. An inter-
nal comparator checks each pin’s voltage versus a threshold of
400mV. If the pin is grounded, it will be below the threshold
and the phase will be disabled. The output impedance of the
PWM pin is approximately 5kΩ. Any external pull-down resis-
tance connected to the PWM pin should not be less than 25kΩ
to ensure proper operation. The phase detection is made during
the first two clock cycles of the internal oscillator. After this
time, if the PWM output was not grounded, it will switch between
0V and 5V. If the PWM output was grounded, it will remain off.
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Since each phase is
monitored independently, operation approaching 100% duty
cycle is possible. Also, more than one output can be on at a time
for overlapping phases.
Master Clock FrequencyThe clock frequency of the ADP3166 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in TPC 1. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
Table I. VID Code vs. Output Voltage11111No CPU
Output Voltage Differential Sensing
The ADP3166 combines differential sensing with a high accu-
racy VID DAC and reference and a low offset error amplifier to
maintain a worst-case specification of ±1% differential sensing
error over its full operating output voltage and temperature
range. The output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
regulation point, usually the remote sense pin of the micropro-
cessor. FBRTN should be connected directly to the remote
sense ground point. The internal VID DAC and precision refer-
ence are referenced to FBRTN, which has a minimal current of
100µA to allow accurate remote sensing. The internal error
amplifier compares the output of the DAC to the FB pin to
regulate the output voltage.
Output Current SensingThe ADP3166 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current, and for current limit detection.
Sensing the load current at the output gives the total average
current being delivered to the load, which is an inherently more
accurate method than peak current detection or sampling the
current across a sense element such as the low-side MOSFET.
ADP3166This amplifier can be configured several ways depending on the
objectives of the system:Output inductor ESR sensing without thermistor for
lowest costOutput inductor ESR sensing with thermistor for improved
accuracy with tracking of inductor temperatureSense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the sensing
element (such as the switch node side of the output inductors) to
the inverting input, CSSUM. The feedback resistor between
CSCOMP and CSSUM sets the gain of the amplifier, and a filter
capacitor is placed in parallel with this resistor. The gain of the
amplifier is programmable by adjusting the feedback resistor to
set the load line required by the microprocessor. The current
information is then given as the difference of CSREF – CSCOMP.
This difference signal is used internally to offset the VID DAC
for voltage positioning, and as a differential input for the current
limit comparator.
To provide the best accuracy for the sensing of current, the
CSA has been designed to have a low offset input voltage. Also,
the sensing gain is determined by external resistors so that it can
be made extremely accurate.
Active Impedance Control ModeFor controlling the dynamic output voltage droop as a function
of output current, a signal proportional to the total output cur-
rent at the CSCOMP pin can be scaled to be equal to the droop
impedance of the regulator times the output current. This droop
voltage is then used to set the input control voltage to the sys-
tem. The droop voltage is subtracted from the DAC reference
input voltage directly to tell the error amplifier where the output
voltage should be. This differs from previous implementations
and allows enhanced feed-forward response.
Voltage Control ModeA high gain-bandwidth voltage mode error amplifier is used for
the voltage mode control loop. The control input voltage to the
positive input is set via the VID 5-bit logic code according to
the voltages listed in Table I. This voltage is also offset by the
droop voltage for active positioning of the output voltage as a
function of current, commonly known as active voltage position-
ing. The output of the amplifier is the COMP pin, which sets
the termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the output sense location with
a resistor, RB, and is used for sensing and controlling the output
voltage at this point. A current source from the FB pin flowing
through RB is used for setting the no-load offset voltage from
the VID voltage. The no-load voltage will be positive with respect
to the VID DAC. The main loop compensation is incorporated
in the feedback network between FB and COMP.
Soft StartThe power-on ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-off
time, as explained in the following section. In UVLO or when
EN is a logic low, the DELAY pin is held at ground. After the
UVLO threshold is reached and EN is a logic high, the DELAY
capacitor is charged up with an internal 20µA current source.
The output voltage follows the ramping voltage on the DELAY
pin, limiting the inrush current. The soft start time depends on
the value of VID DAC and CDLY, with a secondary effect from
RDLY. Refer to the Applications section for detailed information
on setting CDLY.
When the PWRGD threshold is reached, the soft start cycle is
stopped and the DELAY pin is pulled up to 3V. This ensures
that the output voltage is at the VID voltage when the PWRGD
signals to the system that the output voltage is good. If EN is
taken low or if VCC drops below UVLO, the DELAY capacitor
is reset to ground to be ready for another soft start cycle.
Current Limit and Short-Circuit ProtectionThe ADP3166 compares a programmable current limit set point
to the voltage on the output of the current sense amplifier at the
CSCOMP pin. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation, the
voltage on ILIMIT is 3 V. The current through the external
resistor is internally scaled to give a current limit threshold of
10.4mV/µA. If the difference in voltage between CSREF and
CSCOMP drops below the current limit threshold, the internal
current limit amplifier will control the internal COMP voltage
to maintain the average output current at the limit.
After the limit is reached, the 3V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3V to 1.8V. The
Applications section discusses the selection of RDLY based on
the CDLY that has been chosen.
Because the controller continues to cycle the phases during the
latch-off delay time, if the short is removed before the 1.8 V
threshold is reached, the controller will return to normal operation.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if short circuit has caused
the output voltage to drop below the PWRGD threshold, then a
soft start cycle is initiated.
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3166, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a large
(greater than 1MΩ) resistor should be connected from VCC to
DELAY. This prevents the DELAY capacitor from discharging
so the 1.8 V threshold is never reached. The resistor will have
an impact on the soft start time because the current through it
will add to the internal 20 µA current source.
During startup when the output voltage is below 200mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This sec-
ondary current limit controls the internal COMP voltage to the
PWM comparators to 2V. This will limit the voltage drop across
the low-side MOSFETs through the current balance circuitry.
Dynamic VIDThe ADP3166 incorporates the ability to dynamically change
the VID input while the controller is running. This allows the
output voltage to change while the supply is running and sup-
plying current to the load. This is commonly referred to as
VID on-the-fly (OTF). A VID-OTF can occur under either
light load or heavy load conditions. The processor signals the
controller by changing the VID inputs in multiple steps from
the start code to the finish code. This change can be either
positive or negative.
When a VID input changes state, the ADP3166 detects the
change and blanks the DAC for a minimum of 400ns. This
time is to prevent a false code due to logic skew while the six
VID inputs are changing. Additionally, the first VID change
initiates the PWRGD blanking function for a minimum of
100µs to prevent a false PWRGD event. Each VID change will
reset the internal timer.
Power Good MonitoringThe power good comparator monitors the output voltage via the
CSREF pin. The PWRGD pin is an open-drain output whose
high level (when connected to a pull-up resistor) indicates that
the output voltage is within the nominal limits specified previ-
ously, based on the VID voltage setting. PWRGD will go low if
the output voltage is outside of this specified range. PWRGD is
blanked during a VID-OTF event for a period of 100µs to
prevent false signals during the time the output is changing.
Output CrowbarAs part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) and the CROWBAR logic output goes
high when the output voltage exceeds the upper power good
threshold. This crowbar action releases once the output volt-
age has fallen back within specifications if no other faults are
present. The release threshold is approximately 400mV.
Turning on the low-side MOSFETs pulls down the output as
the reverse current builds up in the inductors. If the output
overvoltage is due to a short of the high-side MOSFET, this
action current limits the input supply or blow its fuse, protect-
ing the microprocessor from destruction.
The CROWBAR output can be used to signal an external input
crowbar or other protection circuit.
Output Enable and UVLOThe input VCC must be higher than the UVLO threshold and the
EN pin must be higher than its logic threshold for the ADP3166 to
begin switching. IF UVLO is less than the threshold or the EN pin
is a logic low, the ADP3166 is disabled. This holds the PWM
outputs at ground, shorts the DELAY capacitor to ground, and
holds the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected
to the OD pins of the ADP3418 drivers. Because ILIMIT is
grounded, this disables the drivers such that both DRVH and
DRVL are grounded. This feature is important to prevent dis-
charging of the output capacitors when the controller is shut off.
If the driver outputs were not disabled, a negative voltage could
be generated on the output due to the high current discharge of
APPLICATION INFORMATIONThe design parameters for a typical AMD K8 compliant CPU
application are as follows:Input voltage (VIN) = 12 VVID setting voltage (VVID) = 1.500 VDuty cycle (D) = 0.125Maximum static output voltage error (±VSERR) = ±50 mVMaximum dynamic output voltage error (±VDERR) = ±70 mVError voltage allowed for controller and ripple (±VRERR) =20 mVMaximum output current (IO) = 56 AMaximum output current step (�IO) = 24 AStatic output droop resistance (RO) based on:
a) No load output voltage set at upper output
voltage limit.
VONL = VVID + VSERR – VRERR = 1.530 V
b) Full load output voltage set at lower output
voltage limit.VOFL = VVID – VSERR + VRERR = 1.470 VRO = (VONL – VOFL)/ (IO) = (1.530 V – 1.470 V)/(56A) =
1.1 mΩDynamic output droop resistance (ROD) based on:
a) Output current step to no load with output voltage
set at upper output dynamic voltage limit.
VONLD = VVID + VDERR – VRERR = 1.550 V
b) Output voltage prior to load change
(at IOUT = �IO).VOL = VONL – (�IO � RO)= 1.504 VROD = (VONLD – VOL)/ (�IO) = (1.550 V – 1.504 V)/(24A) =
1.9 mΩNumber of phases (n) = 3Switching frequency per phase (fSW) = 330 kHz
Setting the Clock FrequencyThe ADP3166 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and input and output capacitors.
With n = 3 for three phases, a clock frequency of 990 kHz sets
the switching frequency of each phase, fSW, to 330 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. Figure 1 shows that to
achieve a 990 kHz oscillator frequency, the correct value for RT
is 200 kΩ. Alternatively, the value for RT can be calculated using(1)
where 5.83 pF and 1.5 MΩ are internal IC component values.
ADP3166
ENABLE
*SEE THEORY OF
OPERATION
POWER
GOOD
VCC(CORE)
0.8V–1.55V
56A
VCC(CORE) RTN
820�F/2.5V � 8
OSCON SERIES
12m� ESR (EACH)
1N4148WS
VIN 12V
VIN RTN
1.6�H
2200�F/16V � 3
NICHICON PW SERIES
