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ADP3164JRU
5-Bit Programmable 4-Phase Synchronous Buck Controller
REV.0
5-Bit Programmable 4-Phase
Synchronous Buck Controller
FUNCTIONAL BLOCK DIAGRAMFEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Complies with VRM 9.1 with Lowest System Cost
4-Phase Operation at up to 500 kHz per Phase
Quad Logic-Level PWM Outputs for Interface to
External High-Power Drivers
Active Current Balancing between All Output Phases
Accurate Multiple VRM Module Current Sharing
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Total Output Accuracy �0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Enhanced Power Good Output Detects Open Outputs
in Multi-VRM Power Systems
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® 4 Processors
VRM Modules
CS–
CS+
COMP
PWM3
PWM1
PGND
PWM2
VID4VID3VID2VID1
VCC
REF
GND
VID0
SHARE
PWRGD
PWM4
GENERAL DESCRIPTION
The ADP3164 is a highly efficient 4-phase synchronous buck
switching regulator controller optimized for converting a 12 V
main supply into the core supply voltage required by high per-
formance Intel processors. The ADP3164 uses an internal 5-bit
DAC to read a voltage identification (VID) code directly from
the processor, which is used to set the output voltage between
1.1 V and 1.85 V. The ADP3164 uses a current mode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VRM size and
efficiency. The four output phases share the dc output current
to reduce overall output voltage ripple. An active current bal-
ancing function ensures that all phases carry equal portions of
the total load current, even under large transient loads, to mini-
mize the size of the inductors.
The ADP3164 also uses a unique supplemental regulation tech-
nique called active voltage positioning (ADOPT) to enhance
load transient performance. Active voltage positioning results in
a dc/dc converter that meets the stringent output voltage specifi-
cations for high-performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of the
load current so that it is always optimally positioned for a system
transient. The ADP3164 also provides accurate and reliable short
circuit protection, adjustable current limiting, and an enhanced
Power Good output that can detect open outputs in any phase for
single or multi-VRM systems.
The ADP3164 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 20-lead TSSOP package.
ADOPT is a trademark of Analog Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
ADP3164–SPECIFICATIONS1
(VCC = 12 V, IREF = 150 �A, TA = 0�C to 70�C, unless otherwise noted.)
VID INPUTS
OSCILLATOR
ADP3164
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2Guaranteed by design, not tested in production.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC +0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise speciﬁed, all voltages are referenced
to PGND.
ORDERING GUIDE
PIN CONFIGURATION
RU-20
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP3164 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ADP3164
PIN FUNCTION DESCRIPTIONS
Figure 1.Closed-Loop Output Voltage Accuracy Test Circuit
TPC 1. Oscillator Frequency vs. Timing Capacitor (CT)
TPC 2.Supply Current vs. Oscillator Frequency
TPC 3.Output Accuracy Distribution
ADP3164
THEORY OF OPERATION
The ADP3164 combines a current-mode, fixed frequency PWM
controller with multiphase logic outputs for use in a 4-phase syn-
chronous buck power converter. Multiphase operation is important
for switching the high currents required by high performance
microprocessors. Handling the high current in a single-phase
converter would place unreasonable requirements on the power
components such as inductor wire size and MOSFET ON-
resistance and thermal dissipation. The ADP3164’s high side
current sensing topology ensures that the load currents are bal-
anced in each phase, such that no single phase has to carry
more than it’s share of the power. An additional benefit of high
side current sensing over output current sensing is that the
average current through the sense resistor is reduced by the duty
cycle of the converter allowing the use of a lower power, lower
cost resistor. The outputs of the ADP3164 are logic drivers only
and are not intended to directly drive external power MOSFETs.
Instead, the ADP3164 should be paired with drivers such as
the ADP3413.
Table I.Output Voltage vs. VID Code
The frequency of the ADP3164 is set by an external capacitor
connected to the CT pin. The error amplifier and current sense
comparator control the duty cycle of the PWM outputs to main-
tain regulation. The maximum duty cycle per phase is inherently
limited to 25%. While one phase is on, all other phases remain
off. In no case can more than one output be high at any time.
Output Voltage Sensing
The output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (gm) amplifies the difference between the output
voltage and a programmable reference voltage. The reference
voltage is programmed between 1.1 V and 1.85 V by an internal
5-bit DAC, which reads the code at the voltage identification
(VID) pins. (Refer to Table I for the output voltage versus VID
pin code information.)
Active Voltage Positioning
The ADP3164 uses Analog Devices Optimal Positioning Tech-
nology (ADOPT), a unique supplemental regulation technique
that uses active voltage positioning and provides optimal com-
pensation for load transients. When implemented, ADOPT adjusts
the output voltage as a function of the load current, so that it is
always optimally positioned for a load transient. Standard (passive)
voltage positioning has poor dynamic performance, rendering it
ineffective under the stringent repetitive transient conditions
required by high performance processors. ADOPT, however,
provides a bandwidth for transient response that is limited only
by parasitic output inductance. This yields optimal load tran-
sient response with the minimum number of output capacitors.
Reference Output
A 3.0V reference is available on the ADP3164. This reference
is normally used to accurately set the voltage positioning using a
resistor divider to the COMP pin. In addition, the reference can
be used for other functions such as generating a regulated voltage
with an external amplifier. The reference is bypassed with a 1 nF
capacitor to ground. It is not intended to drive larger capacitive
loads, and it should not be used to provide more than 300 µA of
output current.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator are the
main control elements. The free running oscillator ramps betweenV and 3V. When the voltage on the CT pin reaches 3V, the
oscillator sets the driver logic, which sets PWM1 high. During
the ON time of Phase 1, the driver IC turns on the Phase 1 high
side MOSFET. The CS+ and CS– pins monitor the current
through the sense resistor that feeds all of the high side MOSFETs.
When the voltage between the two pins exceeds the threshold
level, the driver logic is reset and the PWM1 output goes low.
This signals the driver IC to turn off the Phase 1 high side
MOSFET and turn on the Phase 1 low side MOSFET. On the
next cycle of the oscillator, the driver logic toggles and sets
PWM2 high. The current is then steered through the second
phase. This cycle continues for each of the PWM outputs.
On each of the following cycles of the oscillator, the outputs
cycle between each of the active PWM outputs. In each case,
the current comparator resets the PWM output low when the
VT1 is reached. The current of each phase is sensed with the
same resistor and the same comparator, so the current is
inherently balanced. As the load current increases, the output
voltage starts to decrease. This causes an increase in the output
of the voltage error amplifier (gm), which in turn leads to an
increase in the current comparator threshold VT1, thus tracking
the load current.
Active Current Sharing
The ADP3164 ensures current balance in all the active phases
by sensing the current through a single sense resistor. During
one phase’s ON time, the current through the respective high
side MOSFET and inductor is measured through the sense
resistor. When the comparator threshold is reached, the high
side MOSFET turns off. On the next cycle the ADP3164
switches to the next phase. The current is measured with the
same sense resistor and the same internal comparator, ensuring
accurate matching. This scheme is immune to imbalances in the
MOSFET’s RDS(ON) and inductor parasitic resistance.
If for some reason one of the phases has a short circuit failure,
the other phases will still be limited to their maximum output
current (one over the total number phases times the total short
circuit current limit). If this is not sufficient to supply the load,
the output voltage will droop and cause the PWRGD output to
signal that the output voltage has fallen out of its specified
range. If one of the phases has an open circuit failure, the
ADP3164 will detect the open phase and signal the problem via
the PWRGD pin (see Power Good Monitoring section).
Current Sharing in Multi-VRM Applications
The ADP3164 includes a SHARE pin to allow multiple VRMs
to accurately share load current. In multiple VRM applications,
the SHARE pins should be connected together. This pin is a
low impedance buffered output of the COMP pin voltage. The
output of the buffer is internally connected to set the threshold
of the current sense comparator. The buffer has a 400 µA sink
current, and a 2 mA sourcing capability. The strong pull-up
allows one VRM to control the current threshold set point for
all ADP3164s connected together. The ADP3164’s high accu-
racy current set threshold ensures good current balance between
VRMs. Also, the low impedance of the buffer minimizes noise
pickup on this trace which is routed to multiple VRMs. This
circuit operates in addition to the active current sharing between
phases of each VRM described above.
Short Circuit Protection
The ADP3164 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the specifications set the
peak current limit.
When the load current exceeds the current limit, the excess
current discharges the output capacitor. When the output volt-
age is below the foldback threshold, VFB(LOW), the maximum
deliverable output current is cut by reducing the current sense
threshold from the current limit threshold, VCS(CL), to the fold-
back threshold, VCS(FOLD). Along with the resulting current
foldback, the oscillator frequency is reduced by a factor of five
when the output is 0 V. This further reduces the average current
in short circuit.
Power Good Monitoring
The power good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nomi-
nal output voltage requested by the VID DAC. PWRGD will go
low if the output is outside this range.
Short circuits in a VRM power path are relatively easy to detect
in applications where multiple VRMs are connected to a com-
mon power plane. VRM power train open failures are not as
easily spotted, since the other VRMs may be able to supply
enough total current to keep the output voltage within the
power good voltage specification even when one VRM is not
functioning. The ADP3164 addresses this problem by monitor-
ing both the output voltage and the switch current to determine
the state of the PWRGD output.
The output voltage portion of the power good monitor domi-
nates; as long as the output voltage is outside the specified
window, PWRGD will remain low. If the output voltage is
within specification, a second circuit checks to make sure that
current is being delivered to the output by each phase. If no
current is detected in a phase for three consecutive cycles, it is
assumed that an open circuit exists somewhere in the power
path, and PWRGD will be pulled low.
Output Crowbar
The ADP3164 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip threshold,
VCROWBAR. This comparator overrides the control loop and sets
both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low side MOSFETs, thus pulling
the output down as the reversed current builds up in the induc-
tors. If the output overvoltage is due to a short of the high side
MOSFET, this action will current-limit the input supply or blow
its fuse, protecting the microprocessor from destruction. The
crowbar comparator releases when the output drops below the
specified reset threshold, and the controller returns to normal
operation if the cause of the overvoltage failure does not persist.
Output Disable
The ADP3164 includes an output disable function that turns off
the control loop to bring the output voltage to 0V. Because an
extra pin is not available, the disable feature is accomplished by
pulling the COMP pin to ground. When the COMP pin drops
below 0.8V, the oscillator stops and all PWM signals are driven
low. This function does not place the part in low current shut-
down and the reference voltage is still available. The COMP
pin should be pulled down with an open drain type of output
capable of sinking at least 2 mA.
ADP3164
1.5k�
1.2nF
COC
600nH
FDB7030L
C11
100pF
26.7k�
VINRTN
VIN12V
1�H270�F/16V x 3
OS-CON SP SERIES
820�F/4V x 13
OS-CON SP SERIES
12m�ESR (EACH)
VCC(CORE)
1.1V – 1.85V
NC = NO CONNECT
Figure 2.80 A Intel VRM 9.1-Compliant CPU Supply Circuit

Partno	Mfg	Dc	Qty	Available	Descript
ADP3164JRU	ADI	N/a	71	avai	5-Bit Programmable 4-Phase Synchronous Buck Controller
ADP3164JRU	AD	N/a	3	avai	5-Bit Programmable 4-Phase Synchronous Buck Controller