ADP3161JR Fast Delivery |IC PHOENIX CO.,LIMITED

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ADP3161JR
4-Bit Programmable 2-Phase Synchronous Buck Controller
aREV. 0
4-Bit Programmable 2-Phase
Synchronous Buck Controller
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output
Capacitors
Active Current Balancing Between Both Output Phases
VRM 8.4-Compatible Digitally Programmable 1.3 V to
2.05 V Output
Dual Logic-Level PWM Outputs for Interface to External
High-Power Drivers
Total Output Accuracy �0.8% Over Temperature
Current-Mode Operation
Short Circuit Protection
Power-Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® III Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3161 is a highly efficient dual output synchronous buck
switching regulator controller optimized for converting a 5 V or
12 V main supply into the core supply voltage required by high-
performance processors such as Pentium® III. The ADP3161
uses an internal 4-bit DAC to read a voltage identification (VID)
code directly from the processor, which is used to set the output
voltage between 1.3 V and 2.05 V. The ADP3161 uses a current
mode PWM architecture to drive two logic-level outputs at a
programmable switching frequency that can be optimized for
VRM size and efficiency. The output signals are 180 degrees out of
phase, allowing for the construction of two complementary buck
switching stages. These two stages share the dc output current
to reduce overall output voltage ripple. An active current bal-
ancing function ensures that both phases carry equal portions
of the total load current, even under large transient loads, to
minimize the size of the inductors.
FUNCTIONAL BLOCK DIAGRAM
VCC
REF
GND
COMP
PWM1
PWM2
PWRGD
CS–
CS+
VID3VID2VID1VID0
The ADP3161 also uses a unique supplemental regulation tech-
nique called active voltage positioning to enhance load transient
performance. Active voltage positioning results in a dc/dc con-
verter that meets the stringent output voltage specifications for
high-performance processors, with the minimum number of
output capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so
that it is always optimally positioned for a system transient. The
ADP3161 also provides accurate and reliable short circuit protec-
tion and adjustable current limiting.
The ADP3161 is specified over the commercial temperature
range of 0°C to 70°C and is available in a 16-lead narrow body
SOIC package.
ADOPT is a trademark of Analog Devices Inc.
Pentium is a registered trademark of Intel Corporation
ADP3161–SPECIFICATIONS1(VCC = 12 V, IREF = 150 �A, TA = 0�C to 70�C, unless otherwise noted.)
REFERENCE
VID INPUTS
ADP3161
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Guaranteed by design, not tested in production.
Speciﬁcations subject to change without notice.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3161 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0°C to 70°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
θJA
Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C/W
Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise speciﬁed, all voltages are referenced
to GND.
PIN CONFIGURATION
R-16A
ORDERING GUIDE
ADP3161
TPC 1.Closed-Loop Output Voltage Accuracy Test Circuit
TPC 2.Oscillator Frequency vs. Timing Capacitor
–Typical Performance Characteristics
TPC 3.Supply Current vs. Oscillator Frequency
TPC 4.Output Accuracy Distribution
Table I.Output Voltage vs. VID Code
THEORY OF OPERATION
The ADP3161 combines a current-mode, ﬁxed frequency PWM
controller with antiphase logic outputs in a controller for a two-
phase synchronous buck power converter. Two-phase operation
is important for switching the high currents required by high
performance microprocessors. Handling the high current in a
single-phase converter would place difﬁcult requirements on the
power components such as inductor wire size, MOSFET ON-
resistance, and thermal dissipation. The ADP3161’s high-side
current sensing topology ensures that the load currents are
balanced in each phase, such that neither phase has to carry
more than half of the power. An additional beneﬁt of high-
side current sensing over output current sensing is that the
average current through the sense resistor is reduced by the duty
cycle of the converter, allowing the use of a lower power, lower
cost resistor. The outputs of the ADP3161 are logic drivers only
and are not intended to directly drive external power MOS-
FETs. Instead, the ADP3161 should be paired with drivers such
as the ADP3412, ADP3413, or ADP3414. A system level block
diagram of a 2-phase power supply for high current CPUs is
shown in TPC 5.
The frequency of the ADP3161 is set by an external capacitor
connected to the CT pin. Each output phase of the ADP3161
operates at half of the frequency set by the CT pin. The error
ampliﬁer and current sense comparator control the duty cycle of
the PWM outputs to maintain regulation. The maximum duty
cycle per phase is inherently limited to 50% because the PWM
outputs toggle in two-phase operation. While one phase is on,
the other phase is off. In no case can both outputs be high at the
same time.
Output Voltage Sensing
The output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error ampliﬁer (gm) ampliﬁes the difference between the output
voltage and a programmable reference voltage. The reference
Active Voltage Positioning
The ADP3161 uses Analog Devices Optimal Positioning Technol-
ogy (ADOPT), a unique supplemental regulation technique that
uses active voltage positioning and provides optimal compensa-
tion for load transients. When implemented, ADOPT adjusts the
output voltage as a function of the load current, so that it is always
optimally positioned for a load transient. Standard (passive) volt-
age positioning has poor dynamic performance, rendering it
ineffective under the stringent repetitive transient conditions
required by high performance processors. ADOPT, however,
provides optimal bandwidth for transient response that yields
optimal load transient response with the minimum number of
output capacitors.
Reference Output
A 3.0V reference is available on the ADP3161. This reference
is normally used to set the voltage positioning accurately using a
resistor divider to the COMP pin. In addition, the reference can be
used for other functions such as generating a regulated voltage
with an external ampliﬁer. The reference is bypassed with a 1nF
capacitor to ground. It is not intended to supply current to large
capacitive loads, and it should not be used to provide more than
1 mA of output current.
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error ampliﬁer and the current comparator are the
main control elements. The voltage at the CT pin of the oscilla-
tor ramps between 0V and 3V. When that voltage reaches 3V,
the oscillator sets the driver logic, which sets PWM1 high. Dur-
ing the ON time of Phase 1, the driver IC turns on the high-side
MOSFET. The CS+ and CS– pins monitor the current through
the sense resistor that feeds both high-side MOSFETs. When
the voltage between the two pins exceeds the threshold level
set by the voltage error amplifier (gm), the driver logic is reset
and the PWM output goes low. This signals the driver IC to turn
off the high-side MOSFET and turn on the low-side MOSFET.
On the next cycle of the oscillator, the driver logic toggles and sets
PWM2 high. On each following cycle of the oscillator, the outputs
toggle between PWM1 and PWM2. In each case, the current
comparator resets the PWM output low when the current compara-
tor threshold is reached. As the load current increases, the output
voltage starts to decrease. This causes an increase in the output
of the gm ampliﬁer, which in turn leads to an increase in the
current comparator threshold, thus programming more current to
be delivered to the output so that voltage regulation is maintained.
Active Current Sharing
The ADP3161 ensures current balance in the two phases by
actively sensing the current through a single sense resistor. During
one phase’s ON time, the current through the respective high-side
MOSFET and inductor is measured through the sense resistor
(R4 in TPC 6). When the comparator (CMP1 in the Functional
Block Diagram) threshold programmed by the gm amplifier is
reached, the high-side MOSFET turns off. In the next cycle the
ADP3161 switches to the second phase. The current is measured
with the same sense resistor and the same internal comparator,
ensuring accurate matching. This scheme is immune to imbalances
in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances.
If for some reason one of the phases fails, the other phase will still
ADP3161
the output voltage will droop and cause the PWRGD output to
signal that the output voltage has fallen out of its speciﬁed range.
Short Circuit Protection
The ADP3161 has multiple levels of short circuit protection to
ensure fail-safe operation. The sense resistor and the maximum
current sense threshold voltage given in the speciﬁcations set the
peak current limit.
When the load current exceeds the current limit, the excess
current discharges the output capacitor. When the output voltage is
below the foldback threshold VFB(LOW), the maximum deliverable
output current is cut by reducing the current sense threshold
from the current limit threshold, VCS(CL), to the foldback
threshold, VCS(FOLD). Along with the resulting current foldback,
the oscillator frequency is reduced by a factor of five when
the output is 0 V. This further reduces the average current in
short circuit.
Power-Good Monitoring
The Power-Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nominal
output voltage requested by the VID DAC. PWRGD will go low if
the output is outside this range.
Output Crowbar
The ADP3161 includes a crowbar comparator that senses when
the output voltage rises higher than the specified trip thresh-
old, VCROWBAR. This comparator overrides the control loop and
sets both PWM outputs low. The driver ICs turn off the high side
MOSFETs and turn on the low-side MOSFETs, thus pulling the
output down as the reversed current builds up in the inductors. If
the output overvoltage is due to a short of the high side MOSFET,
this action will current limit the input supply or blow its fuse,
protecting the microprocessor from destruction. The crowbar
comparator releases when the output drops below the specified
reset threshold, and the controller returns to normal operation if
the cause of the overvoltage failure does not persist.
Output Disable
The ADP3161 includes an output disable function that turns off
the control loop to bring the output voltage to 0V. Because
an extra pin is not available, the disable feature is accomplished
by pulling the COMP pin to ground. When the COMP pin drops
below 0.56V, the oscillator stops and both PWM signals are
driven low. This function does not place the part in a low quiescent
current shutdown state, and the reference voltage is still available.
The COMP pin should be pulled down with an open collector
or open drain type of output capable of sinking at least 2 mA.
APPLICATION INFORMATION
A VRM 8.4–Compliant Design Example
The design parameters for a typical high-performance Intel
Pentium III CPU application designed to meet Intel’s VRM 8.4
FMB specification (see Figure 1) are as follows:
Input Voltage (VIN) = 5 V
Nominal Output Voltage (VOUT) = 1.8 V
Static Output Voltage Tolerance (V∆) = (V+) – (V–) = 40 mV –
(–80 mV) = 120 mV
Average Output Voltage (VAVG) = VOUT + = 1.780 V
Maximum Output Current (IO) = 26 A
Output Current di/dt < 20 A/µs.

Partno	Mfg	Dc	Qty	Available	Descript
ADP3161JR	AD	N/a	22	avai	4-Bit Programmable 2-Phase Synchronous Buck Controller