ADP3167 ,5-Bit Programmable 2-Phase Synchronous Buck ControllerAPPLICATIONSCSDesktop PC Power Supplies for:CMP®Intel Pentium 4 ProcessorsCMP1 CS+AMD Athlon™ Proc ..
ADP3168 ,6-Bit Programmable2 /3/4-Phase Synchronous Buck ControllerGENERAL DESCRIPTIONThe ADP3168 is a highly effi cient multiphase synchronous buck 23SW1switching reg ..
ADP3168JRU-REEL ,6-Bit Programmable2 /3/4-Phase Synchronous Buck ControllerGENERAL DESCRIPTIONThe ADP3168 is a highly effi cient multiphase synchronous buck 23SW1switching reg ..
ADP3168JRU-REEL7 ,6-Bit Programmable2 /3/4-Phase Synchronous Buck ControllerFEATURES FUNCTIONAL BLOCK DIAGRAMSelectable 2-, 3-, or 4-Phase Operation at up to VCC RAMPADJ RT ..
ADP3168JRUZ-REEL ,6-Bit Programmable2 /3/4-Phase Synchronous Buck Controller6-Bit Programmable 2-, 3-, 4-Phase Synchronous Buck Controller*ADP3168
ADP3170JRU ,VRM 8.5 Compatible Single Phase Core ControllerSPECIFICATIONS (VCC = 12 V, I = 150 A, T = 0C to 70C, unless otherwise noted.)REF AParameter Sym ..
AK2305 , Dual PCM CODEC for ISDN TERMINAL ADAPTER
AK2306LV , Dual PCM CODEC for ISDN/VoIP TERMINAL ADAPTER
AK2307LV , SPEECH CODEC for Digital Key telephone (5.0V/3.3V)
AK2358F , Base-band LSI for Europian Cordless Telephones(CTI, CTI)
AK2368 , BASE-BAND LSI FOR CORDLESS TELEPHONES
AK2500B , DS3/STS-1 Analog Line Receiver
ADP3160-ADP3167
5-Bit Programmable 2-Phase Synchronous Buck Controller
REV.B
5-Bit Programmable 2-Phase
Synchronous Buck ControllerADOPT is a trademark of Analog Devices, Inc.
Athlon is a trademark of Advanced Micro Devices, Inc.
Pentium is a registered trademark of Intel Corporation.
FEATURES
ADOPT™ Optimal Positioning Technology for Superior
Load Transient Response and Fewest Output Capacitors
Complies with VRM 9.0 with Lowest System Cost
Active Current Balancing between Both Output Phases
5-Bit Digitally Programmable 1.1 V to 1.85 V Output
Dual Logic-Level PWM Outputs for Interface to External
High Power Drivers
Total Output Accuracy �0.8% over Temperature
Current-Mode Operation
Short Circuit Protection
Power Good Output
Overvoltage Protection Crowbar Protects
Microprocessors with No Additional
External Components
APPLICATIONS
Desktop PC Power Supplies for:
Intel Pentium® 4 Processors
AMD Athlon™ Processors
VRM Modules
GENERAL DESCRIPTIONThe ADP3160 and ADP3167 are highly efficient, dual output,
synchronous buck switching regulator controllers optimized for
converting a 5V or 12V main supply into the core supply voltage
required by high-performance processors, such as Pentium 4 and
Athlon. The ADP3160 uses an internal 5-bit DAC to read a volt-
age identification (VID) code directly from the processor that is
used to set the output voltage between 1.1V and 1.85V. The
devices use a current-mode PWM architecture to drive two logic-
level outputs at a programmable switching frequency that can be
optimized for VRM size and efficiency. The output signals are
180degrees out of phase, allowing for the construction of two
complementary buck switching stages. These two stages share the
dc output current to reduce overall output voltage ripple. An
active current balancing function ensures that both phases carry
equal portions of the total load current, even under large transient
loads, to minimize the size of the inductors. The ADP3160 control
FUNCTIONAL BLOCK DIAGRAM
VCC
REF
GND
COMP
PWM1
PWM2
PWRGD
CS
CS+
VID4VID3VID2VID1VID0loop has been optimized for conversion from 12 V, while the
ADP3167 is designed for conversion from a 5 V supply.
The ADP3160 and ADP3167 also use a unique supplemental
regulation technique called active voltage positioning to enhance
load transient performance. Active voltage positioning results
in a dc/dc converter that meets the stringent output voltage
specifications for high-performance processors, with the minimum
number of output capacitors and smallest footprint. Unlike
voltage-mode and standard current-mode architectures, active
voltage positioning adjusts the output voltage as a function of
the load current so that it is always optimally positioned for a
system transient. They also provide accurate and reliable short
circuit protection and adjustable current limiting.
The ADP3160 is specified over the commercial temperature
range of 0∞C to 70∞C and is available in a 16-lead narrow body
SOIC package.
ADP3160/ADP3167–SPECIFICATIONS1(VCC = 12 V, IREF = 150 �A, TA = 0�C to 70�C,
unless otherwise noted.)VID INPUTS
POWER GOOD COMPARATOR
ADP3160/ADP3167NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Guaranteed by design, not tested in production.
Specifications subject to change without notice.
ADP3160/ADP3167
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3160/ADP3167 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS7FB
8CT
9GND
ABSOLUTE MAXIMUM RATINGS*VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V
Operating Ambient Temperature Range . . . . . . . 0∞C to 70∞C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
�JA
Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125∞C/W
Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81∞C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300∞C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged. Unless otherwise specified, all voltages are referenced
to GND.
PIN CONFIGURATION
ORDERING GUIDE
Figure 1.Closed-Loop Output Voltage Accuracy
Test Circuit
Figure 2.Oscillator Frequency vs. Timing Capacitor
OSCILLATOR FREQUENCY kHz
SUPPLY CURRENT mA
250500750125015001750Figure 3.Supply Current vs. Oscillator Frequency
Figure 4.Output Accuracy Distribution
ADP3160/ADP3167
THEORY OF OPERATIONThe ADP3160 and ADP3167 combine a current-mode, fixed
frequency PWM controller with antiphase logic outputs in a
controller for a 2-phase synchronous buck power converter.
Two-phase operation is important for switching the high currents
required by high-performance microprocessors. Handling the
high current in a single-phase converter would place difficult
requirements on the power components such as inductor wire
size, MOSFET ON resistance, and thermal dissipation. Their
high-side current sensing topology ensures that the load currents
are balanced in each phase, such that neither phase has to carry
more than half of the power. An additional benefit of high-side
current sensing over output current sensing is that the average
current through the sense resistor is reduced by the duty cycle
of the converter, allowing the use of a lower power, lower cost
resistor. The outputs of the ADP3160/ADP3167 are logic
drivers only and are not intended to drive external power
MOSFETs directly. Instead, the ADP3160/ADP3167 should
be paired with drivers such as the ADP3414 or ADP3417. A
system level block diagram of a 2-phase power supply for high
current CPUs is shown in Figure 5.
The frequency of the device is set by an external capacitor
connected to the CT pin. Each output phase operates at half of
the frequency set by the CT pin. The error amplifier and
current sense comparator control the duty cycle of the PWM
outputs to maintain regulation. The maximum duty cycle per
phase is inherently limited to 50% because the PWM outputs
toggle in 2-phase operation. While one phase is on, the other
phase is off. In no case can both outputs be high at the same time.
Output Voltage SensingThe output voltage is sensed at the FB pin allowing for remote
sensing. To maintain the accuracy of the remote sensing, the
GND pin should also be connected close to the load. A voltage
error amplifier (gm) amplifies the difference between the output
voltage and a programmable reference voltage. The reference volt-
age is programmed between 1.1V and 1.85V by an internal 5-bit
DAC that reads the code at the voltage identification (VID) pins.
Refer to Table I for the output voltage versus VID pin code
information.
Active Voltage PositioningThe ADP3160 and ADP3167 use Analog Devices Optimal
Positioning Technology (ADOPT), a unique supplemental
regulation technique that uses active voltage positioning and
provides optimal compensation for load transients. When imple-
mented, ADOPT adjusts the output voltage as a function of the
load current, so that it is always optimally positioned for a load
transient. Standard (passive) voltage positioning has poor dynamic
performance, rendering it ineffective under the stringent repetitive
transient conditions required by high-performance processors.
ADOPT, however, provides optimal bandwidth for transient
response that yields optimal load transient response with the
minimum number of output capacitors.
Reference OutputA 3.0V reference is available and is commonly used to set the
voltage positioning accurately using a resistor divider to the
COMP pin. In addition, the reference can be used for other
functions such as generating a regulated voltage with an external
amplifier. The reference is bypassed with a 1nF capacitor to
ground. It is not intended to supply current to large capacitive
loads, and it should not be used to provide more than 1mA of
output current.
Cycle-by-Cycle OperationDuring normal operation (when the output voltage is regulated), the
voltage-error amplifier and the current comparator are the main
control elements. The voltage at the CT pin of the oscillator ramps
between 0V and 3V. When that voltage reaches 3V, the oscillator
sets the driver logic, which sets PWM1 high. During the ON time
of Phase 1, the driver IC turns on the high-side MOSFET. The CS+
and CS– pins monitor the current through the sense resistor that
feeds both high-side MOSFETs. When the voltage between the
two pins exceeds the threshold level set by the voltage error ampli-
fier (gm), the driver logic is reset and the PWM output goes low.
This signals the driver IC to turn off the high-side MOSFET and
turn on the low-side MOSFET. On the next cycle of the oscillator,
the driver logic toggles and sets PWM2 high. On each following
cycle of the oscillator, the outputs toggle between PWM1 and
PWM2. In each case, the current comparator resets the PWM
output low when the current comparator threshold is reached. As
the load current increases, the output voltage starts to decrease.
This causes an increase in the output of the gm amplifier, which in
turn leads to an increase in the current comparator threshold,
thus programming more current to be delivered to the output so
that voltage regulation is maintained.
Active Current SharingThe ADP3160 and ADP3167 ensure current balance in the two
phases by actively sensing the current through a single sense resistor.
During one phase’s ON time, the current through the respective
high-side MOSFET and inductor is measured through the sense
resistor (R4 in Figure 6). When the comparator (CMP1 in the
Functional Block Diagram) threshold programmed by the gm ampli-
fier is reached, the high-side MOSFET turns off. In the next cycle,
the device switches to the second phase. The current is measured
with the same sense resistor and the same internal comparator,
ensuring accurate matching. This scheme is immune to imbalances
in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances.
If for some reason one of the phases fails, the other phase will
still be limited to its maximum output current (one-half of the
short circuit current limit). If this is not sufficient to supply the
load, the output voltage will droop and cause the PWRGD
output to signal that the output voltage has fallen out of its
specified range.
Short Circuit ProtectionThe ADP3160 and ADP3167 have multiple levels of short
circuit protection to ensure fail-safe operation. The sense resis-
tor and the maximum current sense threshold voltage given in
the specifications set the peak current limit.
Table I.Output Voltage vs. VID CodeWhen the load current exceeds the current limit, the excess current
discharges the output capacitor. When the output voltage is
below the foldback threshold VFB(LOW), the maximum deliverable
output current is cut by reducing the current sense threshold
from the current limit threshold, VCS(CL), to the foldback thresh-
old, VCS(FOLD). Along with the resulting current foldback, the
oscillator frequency is reduced by a factor of 5 when the output isV. This further reduces the average current in short circuit.
Power Good MonitoringThe Power Good comparator monitors the output voltage of the
supply via the FB pin. The PWRGD pin is an open-drain output
whose high level (when connected to a pull-up resistor) indicates
that the output voltage is within the specified range of the nomi-
nal output voltage requested by the VID DAC. PWRGD will go
low if the output is outside this range.
Output CrowbarThe ADP3160 and ADP3167 include a crowbar comparator that
senses when the output voltage rises higher than the specified trip
threshold, VCROWBAR. This comparator overrides the control loop
and sets both PWM outputs low. The driver ICs turn off the
high-side MOSFETs and turn on the low-side MOSFETs, thus
pulling the output down as the reversed current builds up in the
inductors. If the output overvoltage is due to a short of the high-
side MOSFET, this action will current limit the input supply or
blow its fuse, protecting the microprocessor from destruction.
The crowbar comparator releases when the output drops below the
specified reset threshold, and the controller returns to normal
The ADP3160 and ADP3167 include an output disable function
that turns off the control loop to bring the output voltage to 0V.
Because an extra pin is not available, the disable feature is accom-
plished by pulling the COMP pin to ground. When the COMP pin
drops below 0.56V for the ADP3160 and 0.64V for the ADP3167,
the oscillator stops and both PWM signals are driven low. This
function does not place the part in a low quiescent current shut-
down state, and the reference voltage is still available. The COMP
pin should be pulled down with an open collector or open-drain
type of output capable of sinking at least 2mA.
APPLICATION INFORMATION
A VRM 9.0-Compliant Design ExampleThe design parameters for a typical high-performance Intel CPU
application (see Figure 6) are as follows:
Input Voltage (VIN) = 12 V
Nominal Output Voltage (VOUT) = 1.7 V
Static Output Tolerance (V�) = (V+) – (V–) =
0 mV – (–130 mV) = 130 mV
Maximum Output Current (IO) = 53.4 A
Output Current di/di < 50 A/�s
ADP3160/ADP3167
CT Selection—Choosing the Clock FrequencyThe ADP3160 and ADP3167 use a fixed-frequency control archi-
tecture. The frequency is set by an external timing capacitor, CT.
The value of CT for a given clock frequency can be selected using
the graph in Figure 2.
The clock frequency determines the switching frequency, which
relates directly to switching losses and the sizes of the inductors
and input and output capacitors. A clock frequency of 400 kHz
sets the switching frequency of each phase, fSW, to 200 kHz, which
represents a practical trade-off between the switching losses and
the sizes of the output filter components. From Figure 2, for 400 kHz
the required timing capacitor value is 150 pF. For good frequency
stability and initial accuracy, it is recommended to use a capacitor
with a low temperature coefficient and tight tolerance, e.g., an
MLC capacitor with NPO dielectric and with 5% or less tolerance.
Inductance SelectionThe choice of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and the conduction losses in
the MOSFETs, but allows using smaller size inductors and, for
a specified peak-to-peak transient deviation, output capacitors
with less total capacitance. Conversely, a higher inductance
means lower ripple current and reduced conduction losses,
but requires larger size inductors and more output capacitance
for the same peak-to-peak transient deviation. In a 2-phase
converter a practical value for the peak-to-peak inductor ripple
current is under 50% of the dc current in the same inductor.
A choice of 46% for this particular design example yields a total
peak-to-peak output ripple current of 23% of the total dc output
(1)
For 12.5 A peak-to-peak ripple current, which corresponds to
just under 50% of the 26.7 A full-load dc current in an induc-
tor, Equation 1 yields an inductance of:
A 600 nH inductor can be used, which gives a calculated ripple
current of 12.2 A at no load. The inductor should not saturate
at the peak current of 32.8 A and should be able to handle the
sum of the power dissipation caused by the average current of
26.7 A in the winding and the core loss.
The output ripple current is smaller than the inductor ripple
current due to the two phases partially canceling. This can be
calculated as follows:
(2)
Designing an InductorOnce the inductance is known, the next step is either to design
an inductor or find a standard inductor that comes as close as
possible to meeting the overall design goals. The first decision in
designing the inductor is to choose the core material. There are
several possibilities for providing low core loss at high frequen-
cies. Two examples are the powder cores (e.g., Kool-Mm® from
VCC(CORE)
1.1V 1.85V
53.4A
VCC(CORE) RTN
VIN
12V
VIN RTN
26.1k�
20�
100pF
COC
3.3nF
NC = NO CONNECTFigure 6.53.4 A Intel CPU Supply Circuit, VRM 9.0 FMB Design
