ADP3157JR-REEL Fast Delivery |IC PHOENIX CO.,LIMITED

ADP3157JR-REEL ,VRM 8.2/3/4 Buck ControllerSPECIFICATIONSA CC INParameter Symbol Conditions Min Typ Max UnitsOUTPUT ACCURACY1.3 V Output Volta ..
ADP3158 ,4-Bit Programmable Synchronous Buck ControllerSPECIFICATIONS (VCC = 12 V, T = 0C to 70C, unless otherwise noted.)AParameter Symbol Conditions M ..
ADP3158JR ,4-Bit Programmable Synchronous Buck ControllerSPECIFICATIONS (VCC = 12 V, T = 0C to 70C, unless otherwise noted.)AParameter Symbol Conditions M ..
ADP3158JR-REEL ,4-Bit Programmable Synchronous Buck ControllerGENERAL DESCRIPTION standard current-mode architectures, active voltage positioningThe ADP3158 and ..
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ADP3159JRU-REEL ,4-Bit Programmable Synchronous Buck ControllerSPECIFICATIONSAParameter Symbol Conditions Min Typ Max UnitFEEDBACK INPUTOutput Accuracy VFB1.3 V O ..
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ADP3157JR-REEL
VRM 8.2/3/4 Buck Controller
REV.A
5-Bit Programmable Synchronous
Controller for Pentium® III Processors
FUNCTIONAL BLOCK DIAGRAM
PWRGDSENSE+
DRIVE1 DRIVE2 PGND
SENSE–
VCCCT
CMP
VID0
VID2
VID3
VID4
AGND
VID1
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
VRM 8.2, VRM 8.3 and VRM 8.4 Compliant
5-Bit Digitally Programmable 1.3 V to 3.5 V Output
Dual N-Channel Synchronous Driver
Total Output Accuracy 61% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Microprocessors
with No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop PC Power Supplies for:
Pentium II and Pentium III Processor Families
AMD-K6 Processors
VRM Modules
GENERAL DESCRIPTION
The ADP3157 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 5 V main sup-
ply into the core supply voltage required by the Pentium III and
other high performance processors. The ADP3157 uses an
internal 5-bit DAC to read a voltage identification (VID) code
directly from the processor, which is used to set the output
voltage between 1.3 V and 3.5 V. The ADP3157 uses a current
mode, constant off-time architecture to drive two external N-
channel MOSFETs at a programmable switching frequency that
can be optimized for size and efficiency. It also uses a unique
supplemental regulation technique called active voltage position-
ing to enhance load transient performance.
Active voltage positioning results in a dc/dc converter that meets
the stringent output voltage specifications for Pentium II and
Pentium III processors, with the minimum number of output
capacitors and smallest footprint. Unlike voltage-mode and
standard current-mode architectures, active voltage positioning
adjusts the output voltage as a function of the load current so that
it is always optimally positioned for a system transient.
The ADP3157 provides accurate and reliable short circuit pro-
tection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
VCC +12V
VIN +5V
1.3V TO
3.5V
150pF
5-BIT CODE
Figure 1.5-Bit Code Typical Application
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
ADP3157–SPECIFICATIONS(08C £ TA £ +708C, VCC = 12 V, VIN = 5 V, unless otherwise noted)1
OUTPUT VOLTAGE LINE
CT PIN DISCHARGE CURRENT
DRIVER OUTPUT TRANSITION
ERROR AMPLIFIER
ERROR AMPLIFIER
ERROR AMPLIFIER MINIMUM
SHUTDOWN (SD) PIN
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.Dynamic supply current is higher due to the gate change being delivered to the external MOSFETs.The trip point is for the output voltage coming into regulation.
Specifications subject to change without notice.
PIN FUNCTION DESCRIPTIONS
9CT
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS*
Input Supply Voltage (VCC) . . . . . . . . . . . . . .–0.3 V to +16 V
VID0–VID4, SD, PWRGD, CMP, CT . . . . . . .–0.3 V to VCC
DRIVE1, DRIVE2, SENSE+, SENSE– . . . . . .–0.3 V to VCC
Operating Ambient Temperature Range . . . . . .0°C to +70°C
Junction Temperature Range . . . . . . . . . . . . . .0°C to +150°CJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110°C/W
Storage Temperature Range . . . . . . . . . . . .–65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . .+300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3157 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ADP3157VO
1.3V TO
3.5V
0-19A
RTN
VIN +5V
+5V RTN
+12V RTN
VCC +12V
Figure 2.Typical VRM8.2/8.3/8.4 Compliant Core DC/DC Converter Circuit
VCCDRIVE1DRIVE2PGND
AGNDPWRGDSENSE+
SENSE–
CMP
VID0VID1VID2VID3VID4
Figure 3.Functional Block Diagram
OUTPUT CURRENT – Amps
EFFICIENCY – %
1001.42.8144.25.679.811.212.68.4
Figure 4.Efficiency vs. Output
Current
500ns/DIV
DRIVE 1 AND 2 = 5V/DIV
Figure 7.Gate Switching Waveforms
10ms/DIV
Figure 10.Load Transient Response,
1 A–19 A of Figure 2 Circuit
TIMING CAPACITOR – pF100800200300400500600700
FREQUENCY – kHz
300
Figure 5.Frequency vs. Timing
Capacitor
100ns/DIV
Figure 8.Driver Transition
Waveforms
10ms/DIV
Figure 11.Power-On Start-Up
Waveform
OPERATING FREQUENCY – kHz3975883134
SUPPLY CURRENT – mA
Figure 6.Supply Current vs. Oper-
ating Frequency
10ms/DIV
Figure 9.Load Transient Response,
19 A–1 A of Figure 2 Circuit
OUTPUT ACCURACY – %
NUMBER OF PARTS
0.5
Figure 12.Output Accuracy
Distribution, VOUT = 2.0 V
ADP3157
12V
0.1mF
VOUT
Figure 13.Closed-Loop Test Circuit for Accuracy
THEORY OF OPERATION
The ADP3157 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in a
synchronous buck topology. Constant off-time operation offers
several performance advantages, including that no slope com-
pensation is required for stable operation. A unique feature of
the constant-off-time control technique is that since the off-time
is fixed, the converter’s switching frequency is a function of the
ratio of input voltage to output voltage. The fixed off-time is
programmed by the value of an external capacitor connected to
the CT pin. The on-time varies in such a way that a regulated
output voltage is maintained as described below in the cycle-by-
cycle operation. Under fixed operating conditions the on-time
does not vary, and it only varies slightly as a function of load.
This means that switching frequency is fairly constant in stan-
dard VRM applications. In order to maintain a ripple current in
the inductor that is independent of the output voltage (which
also helps control losses and simplify the inductor design), the
off-time is made proportional to the value of the output voltage.
Normally, the output voltage is constant and therefore the off-
time is constant as well.
Active Voltage Positioning
The output voltage is sensed at the SENSE– pin. A voltage-error
amplifier, (gm), amplifies the difference between the output voltage
and a programmable reference voltage. The reference voltage is
programmed to between 1.3 V and 3.5 V by an internal 5-bit
DAC, which reads the code at the voltage identification (VID)
pins. Refer to Table I for output voltage vs. VID pin code infor-
mation. A unique supplemental regulation technique called
active voltage positioning with optimal compensation adjusts
the output voltage as a function of the load current so that it
is always optimally positioned for a load transient. Standard
(passive) load voltage positioning, sometimes recommended for
use with other architectures, has poor dynamic performance
which renders it ineffective under the stringent repetitive tran-
sient conditions specified in Intel VRM documents. Conse-
quently, such techniques do not allow the minimum possible
number of output capacitors to be used. Optimally compensated
active voltage positioning as used in the ADP3157 provides a
bandwidth for transient response that is limited only by parasitic
Table I.Output Voltage vs. VID Code
Cycle-by-Cycle Operation
During normal operation (when the output voltage is regulated),
the voltage-error amplifier and the current comparator (CMPI)
are the main control elements. (See the block diagram of Figure
3.) During the on-time of the high side MOSFET, CMPI moni-
tors the voltage between the SENSE+ and SENSE– pins. When
the voltage level between the two pins reaches the threshold level
VT1, the high side drive output is switched to ground, which
turns off the high side MOSFET. The timing capacitor CT is
then discharged at a rate determined by the off-time controller.
While the timing capacitor is discharging, the low side drive
output goes high, turning on the low side MOSFET. When the
voltage level on the timing capacitor has discharged to the thresh-
old voltage level VT2, comparator CMPT resets the SR flip-flop.
The output of the flip-flop forces the low side drive output to go
low and the high side drive output to go high. As a result, the low
side switch is turned off and the high side switch is turned on.
The sequence is then repeated. As the load current increases, the
output voltage starts to decrease. This causes an increase in the
output of the voltage-error amplifier, which, in turn, leads to an
increase in the current comparator threshold VT1, thus tracking
the load current. To prevent cross conduction of the external

Partno	Mfg	Dc	Qty	Available	Descript
ADP3157JR-REEL \|ADP3157JRREEL	ADI	N/a	1172	avai	VRM 8.2/3/4 Buck Controller