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ADP3156JR-1.8-ADP3156JR-2.5
Fixed Output Buck Controller
REV. 0
Dual Power Supply Controller
for Desktop Systems
FUNCTIONAL BLOCK DIAGRAM
CMPI
VT1
VREF +5%VREF –5%
DELAY
VREF +15%
PWRGDSENSE+
DRIVE1 DRIVE2 PGND
SENSE–
VREF
VCC
VLDO
VT2
CMPTCT
VIN
SENSE–
1.20V
CMP
ADP3156
AGND
FEATURES
Active Voltage Positioning with Gain and Offset
Adjustment
Optimal Compensation for Superior Load Transient
Response
Fixed 1.5 V, 1.8 V and 2.5 V Output Versions
Dual N-Channel Synchronous Driver
On-Board Linear Regulator Controller
Total Output Accuracy 61% Over Temperature
High Efficiency, Current-Mode Operation
Short Circuit Protection
Overvoltage Protection Crowbar Protects Loads with
No Additional External Components
Power Good Output
SO-16 Package
APPLICATIONS
Desktop Computer Supplies
ACPI-Compliant Power Systems
General Purpose DC-DC Converters
GENERAL DESCRIPTIONThe ADP3156 is a highly efficient synchronous buck switching
regulator controller optimized for converting the 3.3 V or 5 V
main supply into lower supply voltages required on the mother-
boards of Pentium® III and other high performance processor
systems. The ADP3156 uses a current mode, constant off-time
architecture to drive two external N-channel MOSFETs at a
programmable switching frequency that can be optimized for
size and efficiency. It also uses a unique supplemental regulation
technique called active voltage positioning to enhance load
transient performance. Active voltage positioning results in a
DC/DC converter that provides the best possible transient re-
sponse using the minimum number of output capacitors and
smallest footprint. Unlike voltage-mode and standard current-
mode architectures, active voltage positioning adjusts the output
voltage as a function of the load current so that it is always
optimally positioned for a system transient.
The ADP3156 provides accurate and reliable short circuit
protection and adjustable current limiting. It also includes an
integrated overvoltage crowbar function to protect the micro-
processor from destruction in case the core supply exceeds the
nominal programmed voltage by more than 15%.
Pentium is a registered trademark of Intel Corporation.
All other trademarks are the property of their respective holders.
Figure 1.Typical Application
The ADP3156 contains a linear regulator controller that is
designed to drive an external N-channel MOSFET. This linear
regulator is used to generate the auxiliary voltages (AGP, GTL,
etc.) required in most motherboard designs, and has been de-
signed to provide a high bandwidth load-transient response. A
pair of external feedback resistors sets the linear regulator out-
put voltage.
ADP3156–SPECIFICATIONSNOTESAll limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. Specifications subject to change without
notice.Dynamic supply current is higher due to the gate charge being delivered to the external MOSFETs.The trip point is for the output voltage coming into regulation.
Specifications subject to change without notice.
(08C # TA # +708C, VCC = 12 V, VIN = 5 V, unless otherwise noted)1
ABSOLUTE MAXIMUM RATINGS*Input Supply Voltage (VCC) . . . . . . . . . . . . . . .–0.3 V to +16 V
Shutdown Input Voltage . . . . . . . . . . . . . . . . –0.3 V to +16 V
Operating Ambient Temperature Range . . . . . . 0°C to +70°C
Junction Temperature Range . . . . . . . . . . . . . . 0°C to +150°CJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C
*This is a stress rating only; operation beyond these limits can cause the device to
be permanently damaged.
ORDERING GUIDE
PIN CONFIGURATION
16-Lead SOIC
PIN FUNCTION DESCRIPTIONS
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADP3156 features proprietary ESD protection circuitry, permanent damage may
ADP3156VO
1.8V
RTN
100kV
5V RTN
12V RTN
1000mF
RTN
12V
VO2
+1.5VFigure 2.ADP3156 Typical VRM8.4 AGP and GTL Chipset DC/DC Converter Circuit
CMPI
VT1
VREF +5%VREF –5%
DELAY
VREF +15%
PWRGDSENSE+
DRIVE1 DRIVE2 PGND
SENSE–
VREF
VCC
VLDO
VT2
CMPTCT
VIN
SENSE–
CMP
ADP3156
AGNDFigure 3.Functional Block Diagram
OUTPUT CURRENT – Amps
EFFICIENCY – %
0.51.52.53.54.56.55.5Figure 4.Efficiency vs. Output
Current
500ns/DIV
DRIVE 1 AND 2 = 5V/DIVFigure 7.Gate Switching Waveforms
Figure 10.Transient Response,
1 A–7 A of Figure 2 Circuit
TIMING CAPACITOR – pF100800200300400500600700
FREQUENCY – kHz
300Figure 5.Frequency vs. Timing
Capacitor
100ns/DIVFigure 8.Driver Transition
Waveforms
10ms/DIVFigure 11.Power-On Start-Up
Waveforms
OPERATING FREQUENCY – kHz3975883134
SUPPLY CURRENT – mAFigure 6.Supply Current vs.
Operating Frequency
10ms/DIVFigure 9.Transient Response,
7 A–1 A of Figure 2 Circuit
ADP3156
12V
0.1mF
VOUTFigure 12. Closed-Loop Test Circuit for Accuracy
THEORY OF OPERATIONThe ADP3156 uses a current-mode, constant-off-time control
technique to switch a pair of external N-channel MOSFETs in a
synchronous buck topology. Constant off-time operation offers
several performance advantages, including that no slope com-
pensation is required for stable operation. A unique feature of
the constant-off-time control technique is that since the off-time
is fixed, the converter’s switching frequency is a function of the
ratio of input voltage to output voltage. The fixed off-time is
programmed by the value of an external capacitor connected to
the CT pin. The on-time varies in such a way that a regulated
output voltage is maintained as described below in the cycle-by-
cycle operation. Under fixed operating conditions the on-time
does not vary, and it varies only slightly as a function of load.
This means that switching frequency is fairly constant in stan-
dard VRM applications. In order to maintain a ripple current in
the inductor, which is independent of the output voltage (which
also helps control losses and simplify the inductor design), the
off-time is made proportional to the value of the output voltage.
Normally, the output voltage is constant and therefore the off-
time is constant as well.
Active Voltage PositioningThe output voltage is sensed at the SENSE– pin. SENSE– is
connected to an internal voltage divider. The output of the
divider is then compared to the internal reference. A unique
supplemental regulation technique called active voltage posi-
tioning with optimal compensation adjusts the output voltage as
a function of the load current so that it is always optimally posi-
tioned for a load transient. Standard (passive) voltage position-
ing, sometimes recommended for use with other architectures,
has poor dynamic performance which renders it ineffective
under the stringent repetitive transient conditions specified in
Intel VRM documents. Consequently, such techniques do not
allow the minimum possible number of output capacitors to be
used. Optimally compensated active voltage positioning, as used
in the ADP3156, provides a bandwidth for transient response
that is limited only by parasitic output inductance. This yields
an optimal load transient response with the minimum number
of output capacitors.
Cycle-by-Cycle Operationmonitors the voltage between the SENSE+ and SENSE– pins.
When the voltage level between the two pins reaches the thresh-
old level VT1, the high side drive output is switched to ground,
which turns off the high side MOSFET. The timing capacitor
CT is then discharged at a rate determined by the off-time con-
troller. While the timing capacitor is discharging, the low side
drive output goes high, turning on the low side MOSFET. When
the voltage level on the timing capacitor has discharged to the
threshold voltage level VT2, comparator CMPT resets the SR
flip-flop. The output of the flip-flop forces the low side drive
output to go low and the high side drive output to go high. As a
result, the low side switch is turned off and the high side switch
is turned on. The sequence is then repeated. As the load current
increases, the output voltage starts to decrease. This causes an
increase in the output of the voltage-error amplifier, which, in
turn, leads to an increase in the current comparator threshold
VT1, thus tracking the load current. To prevent cross conduc-
tion of the external MOSFETs, feedback is incorporated to
sense the state of the driver output pins. Before the low side
drive output can go high, the high side drive output must be
low. Likewise, the high side drive output is unable to go high
while the low side drive output is high.
Power GoodThe ADP3156 has an internal monitor that senses the output
voltage and drives the PWRGD pin of the device. This pin is an
open drain output whose high level (when connected to a pull-
up resistor) indicates that the output voltage has been within a5% regulation band of the targeted value for more than 500 ms.
The PWRGD pin will go low if the output is outside the regula-
tion band for more than 500 ms.
Output CrowbarAn added feature of using an N-channel MOSFET as the syn-
chronous switch is the ability to crowbar the output with the
same MOSFET. If the output voltage is 15% greater than the
targeted value, the ADP3156 will turn on the lower MOSFET,
which will current-limit the source power supply or blow its
fuse, pull down the output voltage, and thus save the micropro-
cessor from destruction. The crowbar function releases at ap-
proximately 50% of the nominal output voltage. For example, if
the output is programmed to 2.0 V, but is pulled up to 2.3 V or
above, the crowbar will turn on the lower MOSFET. If in this
case the output is pulled down to less than 1.0 V, the crowbar
will release, allowing the output voltage to recover to 2.0 V if
the fault condition has been removed.
ShutdownThe ADP3156 has a shutdown (SD) pin that is pulled down by
an internal resistor. In this condition the device functions nor-
mally. This pin should be pulled high to disable the output
drives.
APPLICATION INFORMATIONA number of power conversion requirements must be consid-
ered when designing an ACPI compliant system. In normal
operating mode, 12 V, 5 V and 3.3 V are available from the
main supply. These voltages need to be converted into the
appropriate supply voltages for the Northbridge core, the
Southbridge core and RAMBUS memory, as well as supplies for
