ADP1148AN-3.3 ,InputV: 0.3-20V; 50mA; high efficiency synchronous step-down switching regulator. For notebook and palmtop computers, portable instrumnets, battery operated digital devicesCHARACTERISTICS A IN SHUTDOWN2Parameter Symbol Conditions Min Typ Max UnitsFEEDBACK VOLTAGEADP1148 ..
ADP1148AN-3.3 ,InputV: 0.3-20V; 50mA; high efficiency synchronous step-down switching regulator. For notebook and palmtop computers, portable instrumnets, battery operated digital devicesCHARACTERISTICS (–408C ≤ T ≤ +858C, V = 10 V, V = 0 V, unless otherwise noted. See Figure 17.)A IN ..
ADP1148AR ,High Efficiency Synchronous Step-Down Switching RegulatorsCHARACTERISTICS A IN SHUTDOWN2Parameter Symbol Conditions Min Typ Max UnitsFEEDBACK VOLTAGEADP1148 ..
ADP1148AR ,High Efficiency Synchronous Step-Down Switching RegulatorsCHARACTERISTICS (–408C ≤ T ≤ +858C, V = 10 V, V = 0 V, unless otherwise noted. See Figure 17.)A IN ..
ADP1173 ,Micropower DC-DC ConverterSpecifications subject to change without notice.REV. 0–2–ADP1173ABSOLUTE MAXIMUM RATINGS*PIN CONFIG ..
ADP1173AR ,Micropower DC-DC ConverterSpecifications subject to change without notice.REV. 0–2–ADP1173ABSOLUTE MAXIMUM RATINGS*PIN CONFIG ..
AIVR3K42 , APLUS INTEGRATED CIRCUITS INC
AK002M4-31 , GaAs MMIC Control FET in SOT 143 DC-2.5 GHz
AK130-VS , TCM Integrated Transceiver
AK134-VQ , 2B D TCM Integrated Quad Transceiver
AK2302 , Dual PCM Codec/Filter COMBO LSI
AK2302 , Dual PCM Codec/Filter COMBO LSI
ADP1148AN-3.3
InputV: 0.3-20V; 50mA; high efficiency synchronous step-down switching regulator. For notebook and palmtop computers, portable instrumnets, battery operated digital devices
REV.A
High Efficiency Synchronous
Step-Down Switching Regulators
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Operation From 3.5 V to 18 V Input Voltage
Ultrahigh Efficiency > 95%
Low Shutdown Current
Current Mode Operation for Excellent Line and Load
Transient Response
High Efficiency Maintained Over Wide Current Range
Logic Controlled Micropower Shutdown
Short Circuit Protection
Very Low Dropout Operation
Synchronous FET Switching for High Efficiency
Adaptive Nonoverlap Gate Drives
APPLICATIONS
Notebook and Palmtop Computers
Portable Instruments
Battery Operated Digital Devices
Industrial Power Distribution
Avionics Systems
Telecom Power Supplies
GPS Systems
Cellular Telephones
GENERAL DESCRIPTIONThe ADP1148 is part of a family of synchronous step-down
switching regulator controllers featuring automatic sleep mode
to maintain high efficiencies at low output currents. These
devices drive external complementary power MOSFETs at
switching frequencies up to 250kHz using a constant off-time
current-mode architecture.
+
VIN (5.2V TO 18V)
0V = NORMAL
>1.5V = SHUTDOWN
*COILTRONICS CTX-68-4
**KRL SL-1-C1-0R050LFigure 1.High Efficiency Step-Down ConverterFigure 2.ADP1148-5 Typical Efficiency
The constant off-time architecture maintains constant ripple
current in the inductor, easing the design of wide input range
converters. Current-mode operation provides excellent line and
load transient response. The operating current level is user
programmable via an external current sense resistor.
The ADP1148 incorporates automatic Power Saving Sleep
Mode operation when load currents drop below the level re-
quired for continuous operation. In sleep mode, standby power
is reduced to only about 2 mW at VIN = 10 V. In shutdown,
both MOSFETs are turned off.
TYPICAL APPLICATIONS
LOAD CURRENT – A
0.02 2
EFFICIENCY – %
0.2
ADP1148, ADP1148-3.3, ADP1148-5–SPECIFICATIONS
ELECTRICAL CHARACTERISTICSFEEDBACK VOLTAGE
REGULATED OUTPUT VOLTAGE
CT PIN DISCHARGE CURRENT
DRIVER OUTPUT TRANSITION
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Quality Control methods. Specifications subject to change without notice.TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas:
ADP1148AR, ADP1148AR-3.3, ADP1148AR-5:TJ = TA + (PD × 110°C/W)
ADP1148AN, ADP1148AN-3.3, ADP1148AN-5:TJ = TA + (PD × 70°C/W)Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.The ADP1148 version is tested with external feedback resistors, setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
(08C ≤ TA ≤ +708C,1 VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.)
ADP1148, ADP1148-3.3, ADP1148-5
ELECTRICAL CHARACTERISTICSFEEDBACK VOLTAGE
SHUTDOWN PIN THRESHOLD
NOTESAll limits at temperature extremes are guaranteed via correlation using standard Quality Control method.TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas:
ADP1148AR, ADP1148AR-3, ADP1148AR-5: TJ = TA + (PD × 110°C/W)
ADP1148AN, ADP1148AN-3, ADP1148AN-5: TJ = TA + (PD × 70°C/W)Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. The allowable operating frequency may be limited by power
dissipation at high input voltages.The ADP1148 version is tested with external feedback resistors setting the nominal output voltage to 3.3 V.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGSInput Supply Voltage (Pin 3) . . . . . . . . . . . . . –0.3 V to +20 V
Continuous Output Currents (Pins 1, 14) . . . . . . . . . . 50 mA
Sense Voltages (Pins 7, 8) . . . . . . . . . . . . . . . . –0.3 V to VCC
Operating Temperature Range . . . . . . . . . . . . 0°C to +70°C
Extended Commercial Temperature Range . . –40°C to +85°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . 300°C
(–408C ≤ TA ≤ +858C, VIN = 10 V, VSHUTDOWN = 0 V, unless otherwise noted. See Figure 17.)
ORDERING GUIDE
ADP1148, ADP1148-3.3, ADP1148-5
CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADP1148, ADP1148-3.3, ADP1148-5 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
PIN FUNCTION DESCRIPTIONS9VFB
PIN CONFIGURATIONS
14-Lead Plastic DIP
14-Lead Plastic SO
NC = NO CONNECT
P-DRIVE
SIGNAL GND
POWER GND
N-DRIVE
VIN
SENSE(+)
VFB*
SHUTDOWNINT VCC
ITH
SENSE(–)
*FIXED OUTPUT VERSIONS = SD1
MAXIMUM OUTPUT CURRENT – A
SENSE
– mFigure 3.Selecting RSENSE vs. Maxi-
mum Output Current
OUTPUT CURRENT – A
EFFICIENCY/LOSS – %
0.010.033.00.10.31.0Figure 6.Typical Efficiency Losses
LOAD CURRENT – A
OUT
– mV
–40Figure 9.Load Regulation
Figure 5.Selecting Minimum Output
Capacitor vs. (VIN–VOUT) and Inductor
Figure 8.ADP1148-5 Output Voltage
Change vs. Input Voltage
Figure 11.Supply Current in Shutdown
FREQUENCY – kHz
CAPACITANCE – pFFigure 4.Operating Frequency vs.
Timing Capacitor Value
INPUT VOLTAGE – V
EFFICIENCY – %Figure 7.Efficiency vs. Input Voltage
INPUT VOLTAGE – V
SUPPLY CURRENT – mA
1.0Figure 10.DC Supply Current
(VIN–VOUT) – V
NORMALIZED FREQUENCY46810
1.2Figure 12.Operating Frequency vs.
(VIN–VOUT)
TEMPERATURE – 8C
SENSE VOLTAGE – mV
125Figure 15.Current Sense Threshold
Voltage
OPERATING FREQUENCY – kHz
GATE CHARGE CURRENT – mA205026080110140170200230Figure 13.Gate Charge Supply
Current
Figure 14.Off Time vs. VOUT
ADP1148, ADP1148-3.3, ADP1148-5–Typical Performance Characteristics
APPLICATIONSThe ADP1148 uses a current-mode, constant off-time structure
to switch a pair of external complementary N- and P-channel
MOSFETs. The operating frequency of the device is deter-
mined by the value of the external capacitor connected to the
CT pin.
The output voltage is sensed by an internal voltage divider which is
connected to the Sense(–) pin (ADP1148-3.3 and AD1148-5) or
an external voltage divider returned to VFB (ADP1148). A voltage
comparator V, and a gain block G compare the values of the
divided output voltage with a reference voltage of 1.25 V.
To maximize the efficiency, the ADP1148 automatically switches
between two operational modes, power-saving and continuous.
The Flip-Flop 1 is the main control element when the device is
in its power-saving mode while the gain block is the main con-
trol when the output voltage moves to continuous mode. During
the continuous mode of the PMOS switch on-cycle, the current
comparator C, monitors the voltage between Sense(–) and
Sense(+). When the voltage level reaches the threshold level, the
P drive output is switched to VIN which turns off the P-channel
MOSFET. The timing capacitor CT is now able to discharge at
a rate determined by the off-time controller. The discharge
current is made to be proportional to the value of the output
voltage (measured at the Sense(–) pin) to model the inductor
current which decays at a rate which is proportional to the out-
put voltage. While the timing capacitor is discharging, the N
drive output goes to VIN , turning on the N-channel MOSFET.
When the voltage level on the timing capacitor has discharged to
the threshold voltage level VTH1, comparator T switches setting
Flip-Flop 1. This forces the N drive to go off and the P drive
output low and subsequently turns the P-channel MOSFET on.
The sequence is then repeated. As load current increases, the
output voltage starts to reduce. This results in the output of the
gain circuit increasing the level of the current comparator thresh-
old, thus tracking the load current.
At very low load currents the power-saving sequence will be
interrupted by the Set of Flip-Flop 2, by voltage comparator B,
which also monitors the voltage across RSENSE. When the load
current decreases to half the designed inductor ripple current,
the voltage across RSENSE will reverse polarity. When this hap-
pens, comparator B will set the Q-bar output of Flip-Flop 2,
which will go to logic zero state and interrupt the cycle-by-cycle
operation and inhibit the output FET-driver. The output of the
power supply storage capacitor will slowly be drained by the
load and the output voltage starts decreasing. When this
decreased voltage exceeds the VOS of comparator V, this in turn
will reset Flip-Flop 2, and normal cycle-by-cycle operation will
resume. If the load is very small, it will take a long time for Flip-
Flop 2 to reset, and during that time the oscillator capacitor
may discharge below VTH2. At the point at which the timing
capacitor discharges below VTH2, comparator S trips causing the
internal sleep-bar to go low. The circuit is now in sleep mode
and the N-channel Power MOSFET remains turned off. While
the circuit remains in this mode, a significant amount of the
circuit of the IC is turned off dropping the ground current from
approximately 1.6 mA to a level of 160 μA. In this state the load
current is supplied by the output capacitor. The sleep mode is
To prevent both the external MOSFETs from ever being turned
on simultaneously, feedback is incorporated to sense the state of
the driver output pins.
Before the N drive output can go high, the P drive output must
also be high. Likewise, the P drive output is unable to go low
while the N drive output is high. By utilizing a constant off-time
structure, the device operation is a function of the input voltage.
To limit the effect of frequency variation as the device approaches
dropout, the controller begins to increase the discharge current
as VIN drops below VOUT +1.5 V. While the device is in drop-
out, the P-channel MOSFET is on constantly.
RSENSE Selection For Output CurrentThe choice of RSENSE is based on the required output current.
The ADP1148 current comparator has a threshold range which
extends from 0mV to a maximum of 150 mV/RSENSE. The
current comparator threshold sets the peak of the inductor cur-
rent, yielding a maximum output current IMAX equal to the peak
value less half the peak-to-peak ripple current. The ADP1148
operates effectively with values of RSENSE from 20mΩ to
200mΩ. A graph for selecting RSENSE versus maximum output
current is given in Figure 3. Solving for RSENSE and allowing a
margin for variations in the ADP1148 and external component
values yields:
RSENSE = 100 mV/IMAX
The peak short circuit current, (ISC(PK)) tracks IMAX. Once
RSENSE has been chosen, ISC(PK) can be predicted from the fol-
lowing equation:
ISC(PK) = 150 mV/RSENSE
The load current, below which power-saving mode commences
(IPOWER-SAVING) is determined by the offset in comparator B and
the value of the inductor chosen. Comparator B is designed to
have approximately 5 mV offset. This offset and the inductor
can now be used to predict the power saving mode current as
follows:
IPOWER-SAVING ~ 5 mV/RSENSE + VO × tOFF /2L
The ADP1148 automatically extends tOFF during a short circuit
to provide adequate time for the inductor current to decay be-
tween switch cycles. The resulting ripple current causes the
average short circuit current, ISC(AVG), to be lowered to approxi-
mately IMAX.
L and CT Selection for Operating FrequencyThe ADP1148 uses a constant off-time architecture with tOFF
determined by an external timing capacitor CT. Each time the
P-channel MOSFET switch turns on, the voltage on CT is reset
to approximately 3.3 V. During the off time, CT is discharged by
a current which is proportional to VOUT. The voltage on CT is
analogous to the current in inductor L, which likewise decays at
a rate proportional to VOUT. Therefore, the inductor value must
track the timing capacitor value.
The value of CT is calculated from the preferred continuous
mode operating frequency:
CT = 1/2.6 × 104 × f
Assumes VIN = 2 VOUT (Figure 1 circuit).
ADP1148, ADP1148-3.3, ADP1148-5As the operating frequency is increased, the gate charge losses
will cause reduced efficiency (see Efficiency section). The full
formula for operating frequency is given by:
f = ( 1 – VOUT/VIN)/tOFF
where tOFF = 1.3 × 104 × CT × VREG/VOUT.
VREG is the desired output voltage (i.e., 5 V or 3.3 V), VOUT is
the measured output voltage. Thus, VREG/VOUT = 1 in regulation.
Note that as VIN reduces, the frequency also decreases. When
the input to output voltage differential drops below 1.5 V, the
ADP1148 reduces tOFF by increasing the discharge current in
CT. This prevents audible operation before the device goes into
dropout.
Once the frequency has been set by CT, the inductor L must be
chosen to provide no more than 25 mV/RSENSE of peak-to-peak
inductor ripple current. This is set by the equation:
Substituting for tOFF from above gives the minimum required
inductor value of:
LMIN = 5.1 × 105 × RSENSE × CT × VREG
As the inductor value increases above the minimum value, the
ESR requirements for the output capacitor are relaxed at the
expense of efficiency. If too small an inductor is used, the induc-
tor current will decrease past zero and change polarity. A result
of this occurrence will be that the ADP1148 may not be in
power saving mode operation and efficiency will be significantly
reduced at low currents.
Inductor CoreOnce the minimum value for L is known, the selection of the
inductor must be made. High efficiency converters-π generally
cannot accommodate the core loss found in low cost powdered
iron cores, forcing the use of more expensive ferrite, molypermalloy
(MPP), or Kool Mμ® cores. Actual core loss is independent of
core size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses de-
crease. Unfortunately, increased inductance requires more turns
of wire and therefore copper losses will increase.
Ferrite designs have very low core loss, so design goals can focus
on copper loss and preventing saturation. Ferrite core material
saturates “hard,” which causes the inductance to collapse
abruptly when the peak design current is exceeded. This results
in a sharp increase in inductor ripple current and subsequently
output voltage ripple which can cause the power saving mode
operation to be falsely triggered in the ADP1148. To prevent
this action from occurring, do not allow the core to saturate!
Molypermalloy from Magnetics, Inc., is a very good, low loss
core material for toroids, but it is more expensive than ferrite. A
reasonable compromise from the same manufacturer is Kool
Mμ. Toroids are very space efficient, especially when you can
components are also available from Coiltronics which do not
increase the component height significantly.
Power MOSFETTwo external power MOSFETs must be selected for use with
the ADP1148, a P-channel MOSFET for the main switch, and
an N-channel MOSFET for the synchronous switch. The main
selection parameters for the power MOSFETs are the threshold
voltage VGS(TH) and on resistance RDS(ON).
The minimum input voltage dictates whether standard threshold
or logic-level threshold MOSFETs must be used. For VIN > 8 V,
standard threshold MOSFETs (VGS(TH) < 4 V) may be used. If
VIN is expected to drop below 8 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are strongly recommended. When logic-level
MOSFETs are used, the ADP1148 supply voltage must be less
than the absolute maximum VGS rating for the MOSFETs (e.g.,
>±8 V of IRF7304.
The maximum output current IMAX determines the RDS(ON)
requirement for the two power MOSFETs. When the ADP1148
is operating in continuous mode, the simplifying assumption can
be made that one of the two MOSFETs is always conducting
the average load current. The duty cycles for the MOSFET and
diode are given by:
P-Channel Duty Cycle = VOUT/VIN
N-Channel Duty Cycle = (VIN – VOUT)/VIN
From the duty cycle the required RDS(ON) for each MOSFET
can be derived:
P-Ch RDS(ON) = (VIN × PP)/[VOUT × IMAX2 × (1 + dP)]
N-Ch RDS(ON) = (VIN × PN)/[(VIN – VOUT) × IMAX2 × (1+dN)]
where Pp and PN are the allowable power dissipations and dp and
dN are the temperature dependency of RDS(ON). PP and PN will
be determined by efficiency and/or thermal requirements (see
Efficiency). (1+d) is generally given for a MOSFET in the form
of a normalized RDS(ON) vs. temperature curve, but d = 0.007/°C
can be used as an approximation for low voltage MOSFETs.
The Schottky diode D1 shown in Figure 1 conducts only during
the deadtime between the conduction of the two power
MOSFETs. D1’s purpose is to prevent the body-diode of the
N-channel MOSFET from turning on and storing charge during
the dead time, which could cost as much as 1% in efficiency. D1
should be selected for forward voltage of less than 0.5 V when
conducting IMAX.
CIN and COUT SelectionIn continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle VOUT/VlN. To prevent
large voltage transients, a low ESR input capacitor sized for the
maximum rms current must be used. The maximum rms ca-
pacitor current is given by:
CIN required IRMS ~ [VOUT(VIN – VOUT)]0.5 × IMAX/VIN
This formula has a maximum at VIN = 2 VOUT, where IRMS =
IOUT/2. This simple worst case condition is commonly used for
design because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it advis-
