ADP1043A ,Digital Controller for Isolated Power Supply Applicationsfeatures. The Redundant power supplies 2industry-standard I C bus provides access to the many moni- ..
ADP1108AN-5 ,Micropower DC-DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 VSPECIFICATIONSIN Parameter Symbol Conditions Min Typ Max UnitsQUIESCENT CURRENT I Switch Off 90 150 ..
ADP1108AR ,Micropower DC-DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 VGENERAL DESCRIPTION GAIN BLOCK/LIMERROR AMPThe ADP1108 is a highly versatile micropower switch-mode ..
ADP1108AR ,Micropower DC-DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 VAPPLICATIONSCOMPARATORDRIVERNotebook/Palm Top Computers3 V to 5 V, 5 V to 12 V ConvertersSW2GND FB9 ..
ADP1108AR-12 ,Micropower DC-DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 VFEATURES FUNCTIONAL BLOCK DIAGRAMSOperates at Supply Voltages From 2.0 V to 30 VConsumes Only 110 m ..
ADP1108AR-3.3 ,Micropower DC-DC Converter Adjustable and Fixed 3.3 V, 5 V, 12 VMicropower DC-DC ConverteraAdjustable and Fixed 3.3 V, 5 V, 12 VADP1108
AIVR3K42 , APLUS INTEGRATED CIRCUITS INC
AK002M4-31 , GaAs MMIC Control FET in SOT 143 DC-2.5 GHz
AK130-VS , TCM Integrated Transceiver
AK134-VQ , 2B D TCM Integrated Quad Transceiver
AK2302 , Dual PCM Codec/Filter COMBO LSI
AK2302 , Dual PCM Codec/Filter COMBO LSI
ADP1043A
Digital Controller for Isolated Power Supply Applications
Digital Controller for Isolated
Power Supply ApplicationsADP1043A
FEATURES
Integrates all typical controller functions
Digital control loop
Remote and local voltage sense
Primary and secondary side current sense
PWM control
Synchronous rectifier control
Current sharing
Integrated programmable loop filter 2C interface
Extensive fault detection and protection
Extensive programming
Fast calibration
EEPROM
Standalone or microcontroller control
APPLICATIONS
AC-to-DC power supplies
Isolated dc-to-dc power supplies
Redundant power supplies
Parallel power supplies
Server, storage, network, and communications infrastructure
GENERAL DESCRIPTION The ADP1043A is a secondary side power supply controller IC
designed to provide all the functions that are typically needed in
an ac-to-dc or isolated dc-to-dc control application.
The ADP1043A is optimized for minimal component count,
maximum flexibility, and minimum design time. Features
include remote voltage sense, local voltage sense, primary and
secondary side current sense, pulse-width modulation (PWM)
generation, and hot-swap sense and control. The control loop is
digital with an integrated programmable digital filter. Protection
features include current limiting, ac sense, undervoltage lockout
(UVLO), and overvoltage protection (OVP).
The built-in EEPROM provides extensive programming of the
integrated loop filter, PWM signal timing, inrush current, and
soft start timing and sequencing. Reliability is improved through
a built-in checksum and redundancy of critical circuits.
A comprehensive GUI is provided for easy design of loop filter
characteristics and programming of the safety features. The
industry-standard I2C bus provides access to the many moni-
toring and system test functions.
The ADP1043A is available in a 32-lead LFCSP and operates
from a single 3.3 V supply.
TYPICAL APPLICATION CIRCUIT LOAD
VDDFigure 1.
TABLE OF CONTENTS Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 3
Functional Block Diagram .............................................................. 4
Specifications ..................................................................................... 5
Absolute Maximum Ratings ............................................................ 8
Thermal Resistance ...................................................................... 8
Soldering ........................................................................................ 8
ESD Caution .................................................................................. 8
Pin Configuration and Function Descriptions ............................. 9
Typical Performance Characteristics ........................................... 11
Theory of Operation ...................................................................... 12
Current Sense .............................................................................. 12
Voltage Sense and Control Loop .............................................. 13
ADCs ............................................................................................ 13
Digital Filter ................................................................................ 14
PWM and Sync Rect Outputs (OUTA, OUTB, OUTC,
OUTD, OUTAUX, SR1, SR2) ................................................... 14
Synchronous Rectification ........................................................ 15
Adaptive Dead Time Control.................................................... 15
Light Load Mode ........................................................................ 15
Modulation Limit ....................................................................... 15
OrFET Control (GATE) ............................................................ 15
VDD ............................................................................................. 18
VDD/VCORE OVLO ................................................................ 18
Power Good ................................................................................. 18
Soft Start ...................................................................................... 19
Current Sharing (Share) ............................................................ 20
Power Supply System and Fault Monitoring ............................... 22
Flags .............................................................................................. 22
Monitoring Functions ................................................................ 22
Voltage Readings ........................................................................ 22
Current Readings ........................................................................ 22
Power Readings ........................................................................... 23
Power Monitoring Accuracy ..................................................... 23
First Flag Fault ID and Value Registers ................................... 23
Overtemperature Protection (OTP) ........................................ 23
Overcurrent Protection (OCP) ................................................ 24
Constant Current Mode ............................................................ 25
Overvoltage Protection (OVP) ................................................. 25
Undervoltage Protection (UVP) .............................................. 25
AC Sense (ACSNS)..................................................................... 26
Volt-Second Balance .................................................................. 26
Load Line ..................................................................................... 26
Power Supply Calibration and Trim ............................................ 27
CS1 Trim ...................................................................................... 27
CS2 Trim ...................................................................................... 27
Voltage Calibration and Trim ................................................... 27
Output Voltage Setting (VS3+, VS3− Trim) ........................... 28
VS1 Trim ...................................................................................... 28
VS2 Trim ...................................................................................... 28
RTD/OTP Trim .......................................................................... 28
Layout Guidelines....................................................................... 28
Communication .............................................................................. 29 2C Interface ................................................................................ 29
EEPROM ..................................................................................... 31
Software GUI .............................................................................. 32
Register Listing ............................................................................... 33
Detailed Register Descriptions ..................................................... 35
Fault Registers ............................................................................. 35
Value Registers ............................................................................ 38
Current Sense and Current Limit Registers ............................ 41
Voltage Sense Registers .............................................................. 46
ID Registers ................................................................................. 49
PWM and Synchronous Rectifier Timing Registers ............. 50
Digital Filter Programming Registers ...................................... 58
Adaptive Dead Time Registers ................................................. 60
EEPROM Registers .................................................................... 64
Resonant Mode Operation ............................................................ 65
Resonant Mode Enable .............................................................. 65
PWM Timing in Resonant Mode ............................................. 65
Synchronous Rectification in Resonant Mode ....................... 65
Adjusting the Timing of the PWM Outputs ........................... 66
Frequency Limit Setting ............................................................ 66
ADP1043ALight Load Operation (Burst Mode) ........................................ 66
OUTAUX in Resonant Mode .................................................... 66
Protections in Resonant Mode .................................................. 66
Resonant Mode Register Descriptions ..................................... 67
Outline Dimensions ........................................................................ 71
Ordering Guide ........................................................................... 71
REVISION HISTORY
10/09—Revision 0: Initial Version The ADP1043A is a secondary side controller for switch mode
power supplies (SMPS). It is designed for use in isolated redun-
dant applications. The ADP1043A integrates the typical functions
that are needed to control a power supply. These include Output voltage sense and feedback Digital loop filter compensation PWM generation Current sharing Current, voltage, and temperature sense OrFET control Housekeeping and I2C interface Calibration and trimming
The main function of controlling the output voltage is performed
using the feedback ADCs, the digital loop filter, and the PWM
block. The feedback ADCs use a multipath approach (patent
pending). The ADP1043A combines a high speed, low resolution
(fast and coarse) ADC and a low speed, high resolution (slow and
accurate) ADC. Loop compensation is implemented using the
digital filter. This PID (proportional, integral, derivative) filter is
implemented in the digital domain to allow easy programming
of filter characteristics, which is of great value in customizing
and debugging designs.
The PWM block generates up to seven programmable PWM
outputs for control of FET drivers and synchronous rectification
FET drivers. This programmability allows many traditional and
unique switching topologies to be realized.
A current share bus interface provides for parallel power supplies.
The part also has hot-swap OrFET sense and control for N + 1
redundant power supplies.
Conventional power supply housekeeping features, such as remote
and local voltage sense and primary and secondary side current
sense, are included. An extensive set of protections is offered,
including overvoltage protection (OVP), overcurrent protection
(OCP), overtemperature protection (OTP), undervoltage protec-
tion (UVP), ground continuity monitoring, and ac sense.
All these features are programmable through the I2C bus inter-
face. This bus interface is also used to calibrate the power supply.
Other information, such as input current, output current, and
fault flags, is also available through the I2C bus interface.
The internal EEPROM can store all programmed values and
allows standalone control without a microcontroller. A free,
downloadable GUI is available that provides all the necessary
software to program the ADP1043A. For more information
about the GUI, contact Analog Devices, Inc., for the latest
software and a user guide.
The ADP1043A operates from a single 3.3 V supply and is
specified from −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM RES
SHAREo
VS3–
VS3+
PGOOD1
VDD
ACS
OUTA
OUTB
SR1
SR2
OUTC
OUTD
CS1
PSON
SCL
SDA
VCORE
AGND
OUTAUX
PGOOD2
SHAREi
FLAGIN
DGND
ADCADC
ADC
ADC
UVLO
PWMENGINE
VREF
LDO
ADC
ADC
8kBEEPROM
DIGITAL
CORE
I2CINTERFACE
PWM
ADP1043ASPECIFICATIONS VDD = 3.3 V, TA = −40°C to +85°C, unless otherwise noted. FSR = full-scale range.
Table 1.
ADP1043A Endurance is qualified as per JEDEC Standard 22, Method A117, and is measured at −40°C, +25°C, +85°C, and +125°C. 2 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime derates with junction temperature.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
SOLDERING It is important to follow the correct guidelines when laying out
the PCB footprint for the ADP1043A and when soldering the
part onto the PCB. The AN-772 Application Note discusses this
topic in detail (see ).
ESD CAUTION ADP1043APIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATORVS2AGNDVS1CS2–CS2+ACSNSCS1PGNDSHAREiSHAREoPGOOD1PGOOD2FLAGINPSONSDASCL
TOP VIEW(Not to Scale)
NOTES1.THE ADP1043A HAS AN EXPOSED THERMAL PAD ON THE UNDERSIDEOF THE PACKAGE. FOR INCREASED RELIABILITY OF THE SOLDERJOINTS AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDEDTHAT THE PAD BE SOLDERED TO THE PCB GROUND PLANE.Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Description Power Supply Output Sense Input. This signal is referred to PGND. Input to a low frequency Σ-Δ ADC. Nominal
voltage at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5%
or better to allow for trimming. Analog Ground. This pin is the ground for the analog circuitry of the ADP1043A. Star connect to DGND. Local Voltage Sense Input. This signal is referred to PGND. Input to a high frequency Σ-Δ ADC. Nominal voltage
at this pin should be 1 V. The resistor divider on this input must have a tolerance specification of 0.5% or
better to allow for trimming. Inverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation. When
using high-side current sensing in a 12 V application, place a 110 kΩ resistor between the sense resistor and
this pin. When using low-side current sensing, place a 10 kΩ resistor between the sense resistor and this pin.
When using high-side current sensing, use the formula R = (VCOMMONMODE − 1)/100 μA. A 0.1% resistor must be
used to connect this circuit. Noninverting Differential Current Sense Input. Nominal voltage at this pin should be 1 V for best operation.
When using high-side current sensing in a 12 V application, place a 110 kΩ resistor between the sense resistor
and this pin. When using low-side current sensing, place a 10 kΩ resistor between the sense resistor and this
pin. When using high-side current sensing, use the formula R = (VCOMMONMODE − 1)/100 μA. A 0.1% resistor must
be used to connect this circuit. AC Sense Input. This input is connected upstream of the main inductor through a resistor divider network.
The nominal voltage for this circuit is 0.45 V. This signal is referred to PGND. Primary Side Current Sense Input. This pin is the current transformer input to measure and control the primary
side current. This signal is referred to PGND. The resistors on this input must have a tolerance specification of
0.5% or better to allow for trimming. Power Ground. This pin is the ground connection for the main power rail of the power supply. Star connect
to AGND. Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referred to AGND. Synchronous Rectifier Output. This PWM output connects to the input of a FET driver. This pin can be disabled
when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. PWM Output for Primary Side Switch. This pin can be disabled when not in use. This signal is referred to AGND. Auxiliary PWM Output. This pin can be disabled when not in use. This signal is referred to AGND. OrFET Gate Drive Output (Open Drain). This signal is referred to AGND.
Description Power Supply On Input. This signal is referred to DGND. This is the hardware PSON control signal. It is recom-mended that a 1 nF capacitor be included from the PSON pin to DGND for noise debounce and decoupling. Flag Input. An external signal can be input at this pin to generate a flag condition. Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD2 flag.
This pin is set if any flag is set. Power-Good Output (Open Drain). This signal is referred to AGND. This pin is controlled by the PGOOD1 flag.
This pin is set if any of the following are out of range: power supply, CS1 fast OCP, CS1 accurate OCP, CS2
accurate OCP, UVP, local OVP, or load OVP. Share Bus Output Voltage Pin. Connect this pin to 3.3 V through a 2.2 kΩ resistor. When configured as a digital
share bus, this pin is a digital output. This signal is referred to AGND. Share Bus Feedback Pin. Connect this pin to the SHAREo pin. This signal is referred to AGND. Digital Ground. This pin is the ground for the digital circuitry of the ADP1043A. Star connect to AGND. Output of 2.5 V Regulator. Connect a 100 nF capacitor from this pin to DGND. Positive Supply Input. Range is from 3.1 V to 3.6 V. This signal is referred to AGND. Thermistor Input. A 100 kΩ thermistor is placed from this pin to AGND. This signal is referred to AGND. Address Select Input. Connect a resistor from ADD to AGND. This signal is referred to AGND. Resistor Input. This pin sets up the internal voltage reference for the ADP1043A. Connect a 49.9 kΩ resistor
(±0.1%) from RES to AGND. This signal is referred to AGND. Inverting Remote Voltage Sense Input. There should be a low ohmic connection to AGND. The resistor divider
on this input must have a tolerance specification of 0.5% or better to allow for trimming. Noninverting Remote Voltage Sense Input. This signal is referred to VS3−. Use 0.1% resistors as the resistor
divider to connect this circuit. The resistor divider on this input must have a tolerance specification of 0.5%
or better to allow for trimming. The ADP1043A has an exposed thermal pad on the underside of the package. For increased reliability of the
solder joints and maximum thermal capability, it is recommended that the pad be soldered to the PCB
ground plane.
ADP1043ATYPICAL PERFORMANCE CHARACTERISTICS –40–20020406080
1 ADC ACCU
RACY
TEMPERATURE (°C)1 ADC
ACCURA
TEMPERATURE (°C)
Figure 4. VS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 7. CS1 ADC Accuracy vs. Temperature (from 10% to 90% of FSR)
2 ADC
ACCURA
TEMPERATURE (°C)–40–20020406080
2 ADC AC
CURAC
TEMPERATURE (°C)Figure 5. VS2 ADC Accuracy vs. Temperature (from 10% to 90% of FSR) Figure 8. CS2 ADC Accuracy vs. Temperature (from 0 mV to 200 mV)
HRE
D (
TEMPERATURE (°C)
3 ADC ACC
URACY
(%Figure 9. CS1 Fast OCP Threshold vs. Temperature
THEORY OF OPERATION
CURRENT SENSE The ADP1043A has two individual current sense inputs: CS1
and CS2±. These inputs sense, protect, and control the output
current and the share bus information. They can be calibrated
to remove any errors due to external components.
CS1 Operation (CS1) CS1 is typically used for the monitoring and protection of the
primary side current. This is commonly known as the current
transformer (CT) method of current sensing. The input signal
at the CS1 pin is fed into an ADC for current monitoring. The
range of the ADC is 0 V to 1.38 V. The input signal is also fed
into a comparator for fast OCP protection. The typical config-
uration for the current sense is shown in Figure 10.
1kΩ10ΩI = 100mA
I = 10A
OUTA
OUTB
OUTC
OUTDFigure 10. Current Sense 1 (CS1) Operation
The comparator effectively measures peak current, and the
ADC effectively measures the average current information.
This information is available through the I2C interface. Various
thresholds and limits can be set for CS1, such as OCP. These
thresholds and limits are described in the Current Sense and
Current Limit Registers section.
CS2 Operation (CS2+, CS2−) CS2± is used for the monitoring and protection of the secondary
side current. The full-scale range of the CS2 ADC is 225 mV. The
nominal full load voltage drop can be configured for 37.5 mV,
75 mV, or 150 mV. The differential inputs are fed into an ADC
through a pair of external resistors. When using low-side current
sensing, a 10 kΩ resistor is required. When using high-side current
sensing, a 110 kΩ resistor is required (for a 12 V application).
Low-side current sensing is recommended because it provides
improved performance compared with high-side current sensing.
High-side current sensing is not supported for applications
where the output voltage is above 20 V common mode. (There
is not enough offset trim range above 20 V common mode.)
Typical configurations are shown in Figure 11 and Figure 12.
Various thresholds and limits can be set for CS2, such as OCP.
These thresholds and limits are described in the Current Sense
and Current Limit Registers section.
When not in use, both CS2 inputs should be connected through
10 kΩ resistors to PGND.
110kΩ110kΩ12VFigure 11. High-Side Resistive Current Sense
CS2+CS2–
ADC12 BITS
10kΩ10kΩ
100µA100µAFigure 12. Low-Side Resistive Current Sense (Recommended)
ADP1043AVOLTAGE SENSE AND CONTROL LOOP Multiple voltage sense inputs on the ADP1043A are used for the
monitoring, control, and protection of the power supply output.
The voltage information is available through the I2C interface.
All voltage sense points can be calibrated digitally to remove
any errors due to external components. This calibration can be
performed in the production environment, and the settings can
be stored in the EEPROM of the ADP1043A (see the Power
Supply Calibration and Trim section for more information).
The update rate of the ADC from a control loop standpoint
is set to the switching frequency. Therefore, if the switching
frequency is set to 100 kHz, the ADC outputs a signal every
100 kHz to the control loop. Because the Σ-Δ modulators of the
ADC sample at 1.6 MHz, the output of the ADC is the average
of the 16 readings taken during the 1.6 MHz time frame.
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers are updated every 10 ms. The ADP1043A stores every
ADC sample for 10 ms and then outputs the average value at the
end of the 10 ms period. Therefore, if these registers are read at
least every 10 ms, a true average value is read. The same applies
to the CS1 and CS2 current readings.
For the control loop, the high speed signal always comes from
the VS1 high speed ADC. The low speed signal normally comes
from the VS3 low speed ADC. However, during soft start or in
response to a load OVP or other fault condition, the ADP1043A
can switch its low speed regulating point from VS3 to VS1.
1V
12V12V
11kΩ
1kΩ
LOAD
11kΩ11kΩ
1kΩ1kΩFigure 13. Voltage Sense Configuration
VS1 Operation (VS1) VS1 is used for the monitoring and protection of the power
supply voltage at the output of the LC stage, upstream of the
OrFET. This is also the high frequency feedback loop for the
power supply. The VS1 sense point on the power rail needs an
external resistor divider to bring the nominal common-mode
signal to 1 V at the VS1 pin (see Figure 13). The resistor divider
is necessary because the ADP1043A VS1 ADC input range is
0 V to 1.55 V. This divided-down signal is internally fed into a
high speed and a low speed Σ-Δ ADC. The output of the VS1
ADCs goes to the digital filter.
The high speed ADC has a 2 MHz bandwidth and is run from
a 25 MHz clock. It has a range of ±18 mV. When the sampling
rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise.
Increasing the sampling rate to 400 kHz increases the quanti-
zation noise to 1.2 mV.
In the event of a load overvoltage condition, the power supply
is regulated from the VS1 sense point, rather than from the
VS3 sense point.
VS2 Operation (VS2) VS2 is typically used for the monitoring and protection of the
output of the power supply, downstream of the OrFET. It is
used with VS1 to control the OrFET gate drive turn-on. The
VS2 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS2 pin (see Figure 13). The resistor divider is necessary
because the ADP1043A VS2 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
output of the VS2 ADC goes to the VS2 voltage value register
(Register 0x16).
VS3 Operation (VS3+, VS3−) VS3± is used for the monitoring and protection of the remote
load voltage. It is a fully differential input. This is the main
feedback sense point for the power supply control loop. The
VS3 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS3± pins (see Figure 13). The resistor divider is necessary
because the ADP1043A VS3 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
output of the VS3 ADC goes to the digital filter.
ADCs The ADP1043A includes several ADCs. The high speed ADC is
described in the VS1 Operation (VS1) section. The other ADCs
are low speed, high resolution. They have a 1 kHz bandwidth
and 12-bit resolution. Each ADC has its own voltage reference
for added protection from potential failure. The digital output
of each ADC is readable through the appropriate value register.
DIGITAL FILTER The loop response of the power supply can be changed using
the internal programmable digital filter. A Type 3 filter archi-
tecture has been implemented. To tailor the loop response to
the specific application, the low frequency gain, zero location,
pole location, and high frequency gain can all be set individually
(see the Digital Filter Programming Registers section). It is
recommended that the Analog Devices software GUI be used to
program the filter. The software GUI displays the filter response
in Bode plot format and can be used to calculate all stability
criteria for the power supply.
From the sensed voltage to the duty cycle, the transfer function
of the filter in z-domain is as follows: ⎟⎜×+⎟⎟⎜××=azzc H(z)68.7124.202 (1)
where:
a = filter_pole_register_value/256.
b = filter_zero_register_value/256.
c = high_frequency_gain_register_value.
d = low_frequency_gain_register_value.
m = 1 when 48.8 kHz ≤ fSW < 97.7 kHz.
m = 2 when 97.7 kHz ≤ fSW < 195.3 kHz.
m = 4 when 195.3 kHz ≤ fSW < 390.6 kHz.
m = 8 when 390.6 kHz ≤ fSW.
To go from z-domain to s-domain, plug the following equation
into the H(z) equation: ff z(s)=2
where fSW is the switching frequency.
The digital filter introduces an extra phase delay element into
the control loop. The digital filter circuit sends the duty cycle
information to the PWM circuit at the beginning of each switch-
ing cycle (unlike an analog controller, which makes decisions on
the duty cycle information continuously). Therefore, the extra
phase delay for phase margin, Φ, introduced by the filter block is
Φ = 180 × (fC/fSW)
where:
fC is the crossover frequency.
fSW is the switching frequency.
At one tenth of the switching frequency, the phase delay is 18°.
The GUI incorporates this phase delay into its calculations.
Two sets of registers allow for two distinct filter responses. The
main filter, called the normal mode filter, is controlled by
programming Register 0x60 to Register 0x63. The other filter,
called the light load mode filter, is controlled by programming
Register 0x64 to Register 0x67. The ADP1043A uses the light
load mode filter only when the modulation is below the load
The Analog Devices software GUI allows the user to program
the light load mode filter in the same manner as the normal
mode filter. It is recommended that the GUI be used for this
purpose.
In addition, during the soft start process, a different set of
digital filters is used. The soft start filter value for a, b, and c in
Equation 1 is 0, and the d value is programmed through the soft
start filter gain setting (Register 0x5F[1:0]).
PWM AND SYNC RECT OUTPUTS (OUTA, OUTB,
OUTC, OUTD, OUTAUX, SR1, SR2) The PWM and SR outputs are used for control of the primary
side drivers and the synchronous rectifier drivers. These outputs
can be used for several control topologies, including full-bridge,
phase-shifted ZVS, and interleaved two switch forward converter
configurations. Delays between rising and falling edges can be
individually programmed. Special care must be taken to avoid
shoot-through and cross-conduction. It is recommended that
the Analog Devices software GUI be used to program these
outputs. Figure 14 shows an example configuration to drive a
full-bridge, phase shift topology with synchronous rectification.
SR1
SR2
OUTAOUTC
OUTBOUTDFigure 14. PWM Pin Assignment
The PWM and SR outputs all work together. Therefore, when
reprogramming more than one of these outputs, it is important to
first update all the registers, and then latch the information into
the ADP1043A at one time. During reprogramming, the outputs
are temporarily disabled. A special instruction is sent to the
ADP1043A to ensure that new timing information is programmed
simultaneously. This is done by setting Register 0x5D[0] to 1. It is
recommended that PWM outputs be disabled when not in use.
OUTAUX is an additional PWM output pin; OUTAUX allows
an extra PWM signal to be generated at a different frequency
from the other six PWM outputs. This signal can be used to
drive an extra power converter stage, such as a buck controller
located in front of a full-bridge converter. OUTAUX can also be
used as a clock reference signal.
ADP1043ASYNCHRONOUS RECTIFICATION SR1 and SR2 are recommended for use as the PWM control
signals when using synchronous rectification. These PWM
signals can be set up similarly to the other PWM outputs. The
turn-on of these signals can be programmed in two ways. They
can either be turned on to their full PWM value immediately, or
they can be turned on in a soft start fashion. When turned on
in a soft start, the signals ramp up from zero duty cycle to the
desired duty cycle. The advantage of ramping the SR signals is
to minimize a voltage step that would occur by turning the SR
FETs on completely. The advantage of turning the SR signals
completely on immediately is that they can help to minimize
the voltage transient caused by a load step.
Using Register 0x54[1], the SR soft start can be programmed to
occur just once, the first time that the SR signals are enabled, or
every time that the SR signals are enabled.
When programming the ADP1043A to use SR soft start, ensure
correct operation of this function by setting the falling edge of
SR1 (t10) to a lower value than the rising edge of SR1 (t9) and by
setting the falling edge of SR2 (t12) to a lower value than the
rising edge of SR2 (t11).
The speed of the SR enable is approximately 200 μs. This ensures
that in case of a load step, the SR signals (and any other PWM
outputs that are temporarily disabled) can be turned on quickly
enough to prevent damage to the FETs that they are controlling.
ADAPTIVE DEAD TIME CONTROL A set of registers called the adaptive dead time (ADT) registers
(Register 0x68 to Register 0x6F) allows the dead time between
PWM edges to be adapted on-the-fly. The ADP1043A uses the
ADT only when the modulation is below the dead time (load
current) threshold (programmed in Register 0x68). The Analog
Devices software GUI allows the user to easily program the
dead time values, and it is recommended that the software be
used for that purpose.
Each individual PWM rising and falling edge (t1 to t14) can then
be programmed to have a specific dead time offset. This offset
can be positive or negative. The offset is relative to the nominal
edge position. For example, if t1 has a nominal rising edge of
100 ns and the ADT setting for t1 is −15 ns, t1 moves to 85 ns
when it falls below the adaptive dead time threshold. The dead
times are programmed using Register 0x69 to Register 0x6F.
LIGHT LOAD MODE Register 0x3B allows the ADP1043A to shut down PWM
outputs under light load conditions. The light load current
threshold can be programmed. Below this current threshold,
the SR outputs are disabled. The user can also program any of
the other PWM outputs to shut down below this current thresh-
old. This allows the ADP1043A to be used with an interleaved
two transistor forward topology, incorporating phase shedding
MODULATION LIMIT Using the modulation limit register (Register 0x2E), it is possible to
apply a maximum modulation limit and a minimum modulation
limit to any PWM signal, thus limiting the modulation range of
any PWM. These limits are a percentage of the switching period.
If the modulation required is lower than the minimum setting,
pulse skipping can be enabled.
Following is an example of how to use the modulation limit
settings. In this example, the switching cycle period is 4 μs
and modulation on the t2 edge (falling edge) is enabled. The
nominal position of t2 is set to 1.6 μs, which is 40% of the 4 μs
period. The modulation high limit is set to (nominal + 50%).
Therefore, the modulation high limit is (40% + 50%) = 90% of
the switching cycle period; 90% of 4 μs = 3.6 μs. The modulation
low limit is set to (nominal − 35%). Therefore, the modulation
low limit is (40% − 35%) = 5% of the switching cycle period;
5% of 4 μs = 0.2 μs.
The GUI provided with the ADP1043A is recommended for
evaluating this feature of the ADP1043A (see Figure 15).
Figure 15. Setting Modulation Limits (Modulation Range Shown by Arrows)
OrFET CONTROL (GATE) The GATE control signal drives an external OrFET. The OrFET
gate control is used to protect against power flow into the power
supply from another supply. This ensures that power flows only
out of the power supply and that the unit can be hot-swapped.
The OrFET circuit can be used only when the ADP1043A is
connected to a sense resistor on the low side. The OrFET circuit
is not guaranteed for operation with high-side current sensing.
The GATE pin is an open-drain, N-channel MOSFET. An
external 2.2 kΩ pull-up resistor is recommended. Its output is
normally high to keep the OrFET turned off. When the start-up
criteria have been achieved, the GATE output is pulled low,
allowing the OrFET to turn on. The OrFET turn-on and turn-
off thresholds can be individually programmed. The GATE
outputs are CMOS levels (0 V to 3.3 V). An external driver is
required to turn the OrFET on or off.
The OrFET can be turned off by three methods: Fault flag (any fault flag can be programmed to turn off the
OrFET) Fast OrFET control circuit Accurate OrFET control circuit
Fast OrFET control looks at the reverse voltage across CS2+
and CS2− and is implemented using an analog comparator
(see Figure 16). If the voltage difference between CS2+ and
Recommended Setup Accurate OrFET control also uses the reverse voltage across the
CS2+ and CS2− pins to disable the OrFET (see Figure 16). If the
voltage difference between CS2+ and CS2− is greater than 0 mV,
the OrFET is disabled. The accurate OrFET circuit is more accu-
rate, but it is slower than the fast OrFET circuit.
In a 12 V application, while in normal operating mode When 12 V < VOUT < OVP, use the accurate OrFET control
circuit to turn off the OrFET. When VOUT > OVP, use load OVP to turn off the OrFET. The OrFET turn-on circuit looks at the voltage difference
between VS1 and VS2 (see Figure 16). When the forward
voltage drop from VS1 to VS2 is greater than the program-
mable OrFET enable threshold (Register 0x30[5:4]), the
OrFET is enabled. The OrFET enable threshold can be set to
−0.5%, 0%, 1%, or 2% of the nominal output voltage (12 V).
In a 12 V application, while in light load mode When 12 V < VOUT < OVP, use ACSNS to turn off the
OrFET. When VOUT > OVP, use load OVP to turn off the OrFET.
In a 12 V application, when an internal short circuit occurs,
follow this procedure:
1. Use fast OrFET to turn off the OrFET.
2. Use CS1 OCP or VS1 UVP to shut down the unit and
restart it.
10kΩ10kΩ
RSENSE
11kΩ
1kΩ
12V
11kΩ
1kΩ
VOUT016
ADP1043AOrFET Operation Examples
Hot Plug into a Live Bus A new PSU is plugged into a live 12 V bus (yellow). The internal
voltage VS1 (red) is ramped up before the OrFET is turned on.
After the OrFET is turned on (green), current in the new PSU
begins to flow to the load (blue). The turn-on voltage threshold
between the new PSU and the bus is programmable.
CH2 2.00VCH4 10.0VCH1 2.00VCH3 2.00AM10.0msA CH4 100mVFigure 17. Hot Plug into a Live Bus (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
Runaway Master A rogue PSU on the bus (yellow) has a fault condition, and the
result is that the bus voltage increases above the OVP threshold.
The good PSU turns off the OrFET (green) and regulates its
internal voltage VS1 (red). When the rogue power supply fault
condition is removed, the bus voltage decreases. The OrFET of
the good PSU is immediately turned on and the good PSU
resumes regulating from VS3.
CH2 2.00VCH4 10.0VCH1 2.00VCH3 2.00AM50.0msA CH4 0mVFigure 18. Runaway Master (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Short Circuit When one of the output rectifiers fails, the bus voltage can
collapse if the OrFET is not promptly turned off. The fast
OrFET comparator is used to protect the system from this fault
event. Figure 19 shows a short circuit applied to the output
capacitors, before the OrFET. After the fast OrFET threshold for
CS2 (blue) is triggered, the OrFET (green) is turned off. In this
case, the gate driver is not very fast and takes about 500 ns. (A
larger buffer to drive the OrFET would turn it off quicker.)
Figure 19 also shows the operation when the short circuit is
removed. The internal regulation point, VS1 (red), returns to
12 V, and the OrFET (green) is reenabled. The PSU again begins
to contribute current to the load (blue).
CH2 2.00VCH4 10.0VCH1 2.00VCH3 2.00AM200.0msA CH4 7.5mVFigure 19. Internal Short Circuit (Yellow Is Bus Voltage; Red Is VS1 Voltage;
Green Is OrFET Control Signal; Blue Is Load Current)
Light Load Mode Operation PSU 1 increases its voltage at light load from 12 V to 12.1 V
(yellow). Both PSU 1 and PSU 2 are CCM, so PSU 1 sources
current and PSU 2 sinks current (blue). In PSU 2, after 10 ms
the accurate OrFET control turns off the OrFET to prevent
reverse current from flowing. Note that the OrFET voltage
(green) is solid during this transition because PSU 1 and PSU 2
are in CCM mode.
CH2 2.00VCH4 10.0VCH1 2.00VCH3 2.00AM5.0msA CH4 8.3mVVDD When VDD is applied, a certain time elapses before the part is
capable of regulating the power supply. When the VDD rises
above the power-on reset and UVLO levels, it takes approxi-
mately 20 μs for VCORE to reach its operational point of 2.5 V.
The EEPROM contents are then downloaded to the registers.
The download takes an additional 25 μs (approximately). After
the EEPROM download, the ADP1043A is ready for operation.
If the ADP1043A is programmed to power up at this time, the
soft start ramp begins.
VDD/VCORE OVLO The ADP1043A has built-in overvoltage protection (OVP) on
its supply rails. When the VDD or VCORE voltage rises above
the OVLO threshold, the response can be programmed. This
circuit can be set to be ignored, but it is recommended that the
user not program the OVP circuit to be ignored.
POWER GOOD The ADP1043A has two power-good pins. The PGOOD1 pin
and fault flag are set when any of the following conditions are
out of range: power supply, CS1 fast OCP, CS1 accurate OCP,
CS2 accurate OCP, UVP, local OVP, or load OVP.
The PGOOD2 pin and fault flag are set when any flag is set:
power supply, OrFET, CS1 fast OCP, CS1 accurate OCP, CS2
accurate OCP, voltage continuity, UVP, accurate OrFET disable,
ACSNS, external flag (FLAGIN), VCORE OV, VDD OV, local
OVP, load OVP, OTP, CRC fault, and EEPROM unlocked.
If Register 0x2D[3] is set, PGOOD2 looks only at the flags that
are not programmed to be ignored.
The PGOOD2 pin can also be used as an interrupt pin to notify
a host controller that a flag has been set. The polarity of the
PGOOD1 and PGOOD2 pins is configured as active low.
ADP1043A3. The soft start begins to ramp up the power supply voltage
at the start of Time t2.
SOFT START A dedicated filter is used during soft start. The filter is disabled
at the end of the soft start routine, and the voltage loop digital
filter is used.
4. The ADP1043A keeps the OrFET gate signal turned off.
The voltage differential across the OrFET increases (VS1 −
VS2) due to the diode conduction of the OrFET. When the
voltage differential reaches the OrFET enable threshold
(Register 0x30, Bits[5:4]), the OrFET gate signal is enabled
at Time t3. The ADP1043A begins to regulate voltage from
VS3 instead of VS1.
Fault Condition During Soft Start If a CS1 fast OCP fault condition occurs during soft start, the
entire soft start routine is reset, and the ADP1043A begins another
soft start routine. All other fault flags are ignored during soft start.
5. After the power supply voltage increases above the VS1 UVP
undervoltage limit (Register 0x34, Bits[6:0]), at the end of
Time t4, the UVP flag is reset.
Soft Start Routine When the user turns on the power supply (enables PSON), the
following soft start procedure occurs: 6. After the UVP flag is reset and if all other PGOOD1 fault
conditions are OK, the PGOOD1 signal waits for Time t5
before it is enabled. The length of t5 is programmable in
Register 0x2D, Bits[7:4].
1. The PSON signal is enabled at Time t0. The ADP1043A
checks that initial flags are OK. These flags include VDD
OK and GND OK.
2. The ADP1043A waits for Time t1 before it begins soft start.
The length of t1 is set in Register 0x2C, Bits[4:3].
PSON
VOUT VOLTAGE
(VS1 – VS2) VOLTAGE
SOFT START RAMP
UVPt4t5
120mV021
CURRENT SHARING (SHARE) The ADP1043A supports both analog current sharing and
digital current sharing. It is recommended that analog current
sharing be used because it offers improved performance over
digital current sharing. Digital current sharing requires a load
line of >15 mΩ to prevent oscillation between units. The analog
current sharing scheme has no such issues.
Using Register 0x29, Bit 3, it is possible to program the
ADP1043A to use the CS1 current information or the CS2
current information for current sharing.
Analog Current Sharing The ADP1043A supports analog current sharing. The current
reading from CS1 or CS2 can be output to the SHAREo pin in
the form of a digital bit stream, which is the output of the current
sense ADC (see Figure 23). The bit stream is proportional to the
current being delivered by this unit to the load. By filtering this
digital bit stream using an external RC filter, the current informa-
tion is turned into an analog voltage. This means that there is
now an analog voltage that is proportional to the current being
delivered by this unit to the load. This voltage can be compared
to the share bus. If the unit is not supplying enough current, an
error signal can be applied to the VS3 feedback point. This signal
causes the unit to increase its output voltage and, therefore, its
current contribution to the load.
For more information about the analog current share function-
ality, including schematics and measurements in different fault
and setup conditions, see the product page for the ADP1043A.
Digital Share Bus The digital share bus scheme is similar in principle to the tradi-
tional analog share bus scheme. The difference is that instead of
using a voltage on the share bus to represent current, a digital
word is used.
The ADP1043A outputs a digital word onto the share bus. The
digital word is a function of the current that the power supply is
providing (the higher the current, the larger the digital word).
The power supply with the highest current controls the bus
(master). A power supply that is putting out less current (slave)
sees that another supply is providing more power to the load
than it is. During the next cycle, the slave increases its current
output contribution by increasing its output voltage. This cycle
continues until the slave outputs the same current as the master,
within a programmable tolerance range. Figure 22 shows the
configuration of the digital share bus.
SHAREBUSFigure 22. Digital Current Share Configuration
The digital share bus is based on a single-wire communication
bus principle; that is, the clock and data signals are contained
together.
When two or more ADP1043A devices are connected, they
synchronize their share bus timing. This synchronization is
performed by the start bit at the beginning of a communications
frame. If a new ADP1043A is hot-swapped onto an existing
digital share bus, it waits to begin sharing until the next frame.
The new ADP1043A monitors the share bus until it sees a stop
bit, which designates the end of a share frame. It then performs
synchronization with the other ADP1043A devices during the
next start bit. The digital share bus frame is shown in Figure 24.
BIT STREAM
SHAREo
VOLTAGE
CURRENT
CS2–CS2+8-BIT DATA
2 STOP BITS
(IDLE)
ADP1043AFigure 25 shows the possible signals on the share bus.
LOGIC 1
LOGIC 0
IDLE
PREVIOUSBITNEXTBIT
tBITFigure 25. Share Bus High, Low, and Idle Bits
The length of a bit (tBIT) is fixed at 10 μs. A Logic 1 is defined as
a high-to-low transition at the start of the bit and a low-to-high
transition at 75% of tBIT. A Logic 0 is defined as a high-to-low
transition at the start of the bit and a low-to-high transition at
25% of tBIT.
The bus is idle when it is high during the whole period of tBIT.
All other activity on the bus is illegal. Glitches up to tGLITCH
(200 ns) are ignored.
The digital word that represents the current information is eight
bits long. The ADP1043A takes the eight MSBs of the CS1 or CS2
reading (whichever the user chooses as the current share signal)
and uses this reading as the digital word. When read, the share
bus value at any given time is equal to the CS1 or CS2 current
reading (see Figure 26).
Digital Share Bus Scheme Each power supply compares the digital word that it is outputting
with the digital words of all the other supplies on the bus.
Round 1 In Round 1, every supply first places its MSB on the bus. If a
supply senses that its MSB is the same as the value on the bus, it
continues to Round 2. If a supply senses that its MSB is less than
the value on the bus, it means that this supply must be a slave.
When a supply becomes a slave, it stops communicating on the
share bus because it knows that it is not the master. The supply
then increases its output voltage in an attempt to share more
current.
If two units have the same MSB, they both continue to Round 2,
because either of them could be the master.
Round 2 In Round 2, all supplies that are still communicating on the bus
place their second MSB on the share bus. If a supply senses that
its MSB is less than the value on the bus, it means that this
supply must be a slave and it stops communicating.
Round 3 to Round 8 The same algorithm is repeated for up to eight rounds to allow
supplies to compare their digital words and, in this way, to
determine whether each unit is the master or a slave.
Digital Share Bus Configuration The digital share bus can be configured in various ways.
The bandwidth of the share bus loop is programmable in
Register 0x29[2:0]. The extent to which a slave tries to match
the current of the master can be selected by programming
Register 0x2A[3:0]. The primary side or the secondary side
can be used as the current share signal by programming
Register 0x29[3].
A load line may be required between PSUs when using a digital
share bus. A minimum impedance of 15 mΩ is recommended
between the remote voltage sense node and the load.
8-BITWORD
0x8FFigure 26. How the Share Bus Generates the Digital Word to Place on the Digital Share Bus
POWER SUPPLY SYSTEM AND FAULT MONITORING The ADP1043A has extensive system and fault monitoring
capabilities. The system monitoring functions include voltage,
current, power, and temperature readings. The fault conditions
include out-of-limit values for current, voltage, power, and tem-
perature. The limits for the fault conditions are programmable.
The ADP1043A has an extensive set of flags that are set when
certain thresholds or limits are exceeded. These thresholds and
limits are described in the Fault Registers section.
FLAGS The ADP1043A has an extensive set of flags that are set when
certain limits, conditions, and thresholds are exceeded. The
real-time status of these flags can be read in Register 0x00 to
Register 0x03. The response to these flags is individually
programmable. Flags can be ignored or used to trigger tasks
such as turning off certain PWM outputs or the OrFET GATE
output. Flags can also be used to turn off the power supply. The
ADP1043A can be programmed to respond when these flags are
reset. For more information, see Register 0x08 to Register 0x0D.
The ADP1043A also has a set of latched fault registers
(Register 0x04 to Register 0x07). The latched fault registers
have the same flags as Register 0x00 to Register 0x03, but the
flags in the latched registers remain set so that intermittent
faults can be detected. Reading a latched register resets all the
flags in that register.
MONITORING FUNCTIONS The ADP1043A monitors and reports several signals, including
voltages, currents, power, and temperature. All these values are
stored in individual registers and can be read through the I2C
interface. See the Value Registers section for more details.
VOLTAGE READINGS The VS1, VS2, and VS3 ADCs have an input range of 1.55 V.
The outputs of the ADCs are 12-bit values, which means that
the LSB size is 1.55 V/4096 = 378.4 μV. The user is limited to an
input range of 1.5 V, which means that the ADC output code is
limited to 1.5 V/378.4 μV = 3964.
The equation to calculate the ADC code at a certain voltage
(Vx) is given by the following formula:
ADC Code = Vx/378.4 μV
For example, when there is 1 V on the input of the ADC
ADC Code = 1 V/378.4 μV
ADC Code = 2643
In a 12 V application, the 12 V reading is divided down using
a resistor divider network to provide 1 V at the sense pin.
Therefore, to convert the register value to a real voltage, use
the following formula:
In a 12 V system, this equates to
VOUT = (VSx_Voltage_Value/2643) × 12 V
CURRENT READINGS
CS1 Pin
DC Input Voltage The CS1 ADC is identical in design to the VS1, VS2, and VS3
ADCs. Therefore, the description in the Voltage Readings section
also applies to the CS1 ADC. When there is exactly 1 V on the
CS1 pin, the value in the CS1 value register (Register 0x13)
reads 2968.
CS1 has an input range of 1.38 V. The ADC performs a 12-bit
reading conversion on this value, which means that the LSB size
is 1.38 V/4096 = 337 μV.
The equation to calculate the ADC code at a certain CS1 input
voltage (Vx) is given by the following formula:
ADC Code = Vx/337 μV
For example, when there is 1 V on the CS1 input pin
ADC Code = 1 V/337 μV
ADC Code = 2968
AC Input Voltage CS1 often receives a rectified ac signal through a current
transformer. In this case, the ADC has a frequency response
(see Figure 27).
1011k10k100k
AD
C F
RE
RCE
DE
N (
CS1 INPUT FREQUENCY (Hz)Figure 27. CS1 ADC Frequency Response
To compensate for this frequency response, the multiplication
factor (M) should be used, as shown in the following equation:
M = (−2 × 10−18 × fSW3) + (2 × 10−12 × fSW2) + (2 × 10−8 × fSW) + 0.9998
where fSW is the switching frequency of the power supply.
Using the multiplication factor (M) results in a more accurate
reading. This formula can be used by an MCU or other system
ADP1043ACS2 Pin The user sets the full-scale (FS) voltage drop—37.5 mV,
75 mV, or 150 mV—that is present across the RSENSE resistor
by programming Register 0x23, Bits[7:6].
The CS2 ADC has an input range of 250 mV. The resolution is
12 bits, which means that the LSB size is 250 mV/4096 = 61.04 μV.
The user is limited to an input range of 215 mV.
The equation to calculate the ADC code at a certain voltage
(VX) is given by the following formula:
ADC Code = VX/250 mV × 4096
For example, when there is 150 mV on the input of the ADC
ADC Code = 150 mV/250 mV × 4096
ADC Code = 2457
Therefore, to convert the CS2 value reading to a real current,
use the following formula:
IOUT = (CS2_Value/2457) × (FS/RSENSE)
where:
FS is the full-scale voltage drop (37.5 mV, 75 mV, or 150 mV).
RSENSE is the sense resistor value.
For example, if CS2_Value = 1520, RSENSE = 20 mΩ, and
FS = 150 mV, the real current is calculated as follows:
IOUT = (1520/2457) × (150 mV/20 mΩ)
IOUT = 4.64 A
POWER READINGS The output power value register (Register 0x19) is the product
of the VS3 voltage value and the CS2 current value. Therefore,
a combination of the formulas in the Voltage Readings section
and the CS2 Pin section is used to calculate the power reading
in watts. This register is a 16-bit word. It multiplies two 12-bit
numbers and discards the eight LSBs.
POUT = (VOUT) × (IOUT)
For example,
POUT = (12 V) × (4.64 A) = 55.68 W
POWER MONITORING ACCURACY The ADP1043A power monitoring accuracy is specified relative
to the full-scale range of the signal that it is measuring.
FIRST FLAG FAULT ID AND VALUE REGISTERS When the ADP1043A registers several fault conditions, it stores
the value of the first fault in a dedicated register. For example, if
the overtemperature (OTP) fault is registered, followed by an
OVP fault, the OTP flag is stored in the first flag ID register
(Register 0x10). This register gives the user more information
for fault diagnosis than a simple flag. The contents of this register
are latched, meaning that they are stored until read by the user.
The contents are also reset by a PSON signal.
If a flag is set to be ignored, it does not appear in the first flag
register.
EXTERNAL FLAG INPUT (FLAGIN PIN) The FLAGIN pin can be used to send an external fault
signal into the ADP1043A. The reaction to this flag can
be programmed in the same way as the internal flags.
TEMPERATURE READINGS (RTD PIN) The RTD pin is set up for use with an external 100 kΩ negative
temperature coefficient (NTC) thermistor. The RTD pin has an
internal 10.8 μA current source. Therefore, with a 100 kΩ therm-
istor, the voltage on the RTD pin is 1 V at 25°C. An ADC on the
ADP1043A monitors the voltage on the RTD pin.
RTDNTCFigure 28. RTD Pin Internal Details
The output of the RTD ADC is linearly proportional to the
voltage on the RTD pin. However, thermistors exhibit a non-
linear function of resistance vs. temperature. Therefore, it is
necessary to perform some postprocessing on the RTD ADC
reading to accurately read the temperature. This postprocessing
can be in the form of a lookup table or polynomial equation to
match the specific NTC being used.
OVERTEMPERATURE PROTECTION (OTP) If the temperature sensed at the RTD pin exceeds the program-
mable threshold, the OTP flag is set. The hysteresis on this flag
is 16 mV (see Register 0x2F in Table 43 for details). The response
to the OTP flag is programmable.
The RTD trim is required to make accurate temperature readings
at the lower end of the RTD ADC range. This results in a more
accurate measurement for determining the OTP threshold (see
the RTD/OTP Trim section).
CS1 accurate OCP is used for more precise control of over-
current protection. With CS1 accurate OCP, the reading at
the output of the CS1 ADC (Register 0x13) is compared to a
programmable OCP value. The CS1 accurate OCP value can
be programmed from 0 to 31 decimal using Register 0x22,
Bits[4:0]. If the CS1 reading exceeds the CS1 accurate OCP
value, the CS1 accurate OCP flag is set. The speed of this
decision is 10 ms. The response to the flag is programmable.
OVERCURRENT PROTECTION (OCP) The ADP1043A has several OCP functions. CS1 and CS2 have
individual OCP circuits to provide both primary and secondary
side protection.
CS1 has two protection circuits: CS1 fast OCP and CS1 accurate
OCP (see Figure 29). CS1 fast OCP is an analog comparator.
When the voltage at the CS1 pin exceeds the (fixed) 1.2 V thresh-
old, the CS1 fast OCP flag is set. A blanking time can be set to
ignore the current spike at the beginning of the current signal. A
debounce time can be programmed to improve the noise immunity
of the OCP circuit. When the CS1 fast OCP comparator is set,
all PWM outputs are immediately disabled for the remainder of
the switching cycle. They are reenabled at the start of the next
switching cycle. This function can be bypassed if not needed.
CS2 has one OCP protection circuit: CS2 accurate OCP. The read-
ing at the output of the CS2 ADC (Register 0x18) is compared
to a programmable OCP threshold. The CS2 OCP threshold
can be programmed from 0 to 254 decimal using Register 0x26,
Bits[7:0]. If the CS2 reading exceeds the CS2 OCP threshold,
the CS2 accurate OCP flag is set. The speed of this decision is
10 ms. The response to the flag is programmable.
OUTA
OUTB
OUTC
OUTD
FLAGIN
OUTA
OUTB
OUTC
OUTD
SR1
SR2
OUTAUXFigure 29. CS1 OCP Detailed Internal Schematic
ADP1043ACONSTANT CURRENT MODE The ADP1043A can be configured to operate in constant
current mode. The threshold to enter constant current mode
operation is 10% current below the CS2 accurate OCP setting.
Below this current, the part operates normally, using the output
voltage as the feedback signal for closed-loop operation.
When the ADP1043A reaches the constant current mode
threshold, a flag is set. The CS2 current reading is used instead
of the output voltage as the feedback signal for closed-loop
operation. The output voltage is ramped down linearly to 60%
of its nominal value as the load resistance decreases to ensure
that the current remains constant.
When the control loop reaches 60% of VOUT, the part again uses
the output voltage to close the loop, but at the reduced level
(60% of nominal). If the load resistance continues to decrease,
the current may rise again in this region, up to the CS2 OCP
level, but the voltage is kept limited to 60% of nominal (see
Figure 30). The UVP or CS2 OCP flags can be used to program
a shutdown action.
VOUT NOMINAL
VOUT × 60%
IOUT
OCP
OCP × 90%Figure 30. Constant Current Mode (VOUT vs. IOUT)
OVERVOLTAGE PROTECTION (OVP) The ADP1043A has two OVP circuits. If the output voltage at
the VS1, VS2, or VS3 pin exceeds the programmable threshold
for that pin, that OVP flag is set; the response to that flag can be
programmed. VS1 has one OVP circuit. VS2 and VS3 share the
other OVP circuit. The OVP circuits can be programmed for
different OVP thresholds. See Register 0x32 and Register 0x33
for more information. The formula to set the OVP threshold
voltage is given by
VSx OVP = [(89 + VS1_OVP_Setting)/128] × 1.55 V
For example, when the VS1 OVP setting = 10, then
VS1 OVP = [(89 + 10)/128] × 1.55 V = 1.2 V
UNDERVOLTAGE PROTECTION (UVP) If the voltage being sensed at the VS1 pin goes below the pro-
grammable UVP threshold, the UVP flag is set. Exceptions
to this rule (called undervoltage blanking) include during
startup and when ACSNS is not within limits. The response
to the UVP condition is programmable (see Register 0x34 in
Table 48 for more information).
Also note that the ADP1043A assumes that the CS1 current
pulse signal that it sees first in each cycle is related to OUTB,
and that the second current pulse signal in each cycle is related
to OUTD. If the first current pulse signal is smaller than the
second, OUTB is increased and OUTD is decreased. If the first
current pulse signal is greater than the second, OUTB is
decreased and OUTD is increased.
AC SENSE (ACSNS) The ACSNS circuit performs multiple monitoring functions.
It determines indirectly whether the primary side input voltage
is present, as well as monitoring whether a switching waveform
is present at the output of the synchronous rectifier stage (or
rectifier diodes). The output of the synchronous rectifier stage
(or rectifier diodes) is connected to this pin through an external
resistor divider network.
LOAD LINE The ADP1043A can optionally introduce a digital load line into
the power supply. This option is programmed in the load line
impedance register (Register 0x36). This feature can be used for
advanced current sharing techniques. By default, the load line is
disabled. The load line is introduced digitally, and its slope can
be programmed. It works by taking the CS2 current reading and
adjusting the output voltage accordingly. A load line of up to
51.5 mΩ can be chosen. Figure 31 shows the load line results
using the ADP1043A evaluation board. The evaluation board
uses a 10 mΩ RSENSE resistor.
The ACSNS circuit within the ADP1043A has a comparator
that checks for a signal of 0.45 V or greater every switching
cycle. For example, if the switching frequency is set to 200 kHz,
the switching cycle is 5 μs. The comparator timeout is therefore
set to 5 μs to match the switching cycle. If the comparator does
not trip during the 5 μs interval, the ACSNS flag is set.
VOLT-SECOND BALANCE The ADP1043A has a dedicated circuit to maintain volt-second
balance in the main transformer when operating in full-bridge
topology. This means that a dc blocking capacitor is not necessary.
10020406080100120
(%
RSENSE VOLTAGE DROP (mV)The circuit monitors the dc current flowing in both halves of
the full bridge and stores this information. It compensates the
PWM drive signals to ensure equal current flow in both halves
of the full bridge. The input is through the CS1 pin. Several switch-
ing cycles are required for the circuit to operate effectively. The
volt-second balance places up to 80 ns of modulation on the
OUTB and OUTD pins.
Note that the compensation of the PWM drive signals is per-
formed on t4 (OUTB) and t8 (OUTD) only. Therefore, it is
necessary to use these pins as the modulating PWM signals
for the feature to operate correctly.
The SR1 and SR2 rising edges (t9 and t11) can also be indepen-
dently set to modulate due to the volt-second balance circuit.
The SR1 rising edge (t9) modulates in the same direction as the
OUTB falling edge (t4); the SR2 rising edge (t11) modulates in the
same direction as the OUTD falling edge (t8).
Figure 31. Load Line Settings
ADP1043APOWER SUPPLY CALIBRATION AND TRIM The ADP1043A allows the entire power supply to be calibrated
and trimmed digitally in the production environment. It can
calibrate items such as output voltage and trim for tolerance
errors introduced by sense resistors and resistor dividers, as well
as its own internal circuitry. The part comes factory trimmed,
but it can be retrimmed by the user to compensate for the errors
introduced by external components.
The ADP1043A allows the user enough trim capability to trim
for external components with a tolerance of 0.5% or better. If
the ADP1043A is not trimmed in the production environment,
it is recommended that components with a 0.1% tolerance be
used for the inputs to CS1, CS2, VS1, VS2, VS3+, and VS3− to
meet data sheet specifications.
CS1 TRIM
Using a DC Signal A known voltage (Vx) is applied at the CS1 pin. The CS1 ADC
should output a digital code equal to Vx/337 μV. The CS1 gain
trim register (Register 0x21) is adjusted until the CS1 ADC
value in Register 0x13 reads the correct digital code.
Using an AC Signal A known current (Ix) is applied to the PSU input. This current
passes through a current transformer, a diode rectifier, and an
external resistor (RCS1) to convert the current information to a
voltage (Vx). This voltage is fed into the CS1 pin. The voltage
(Vx) is calculated as follows:
Vx = Ix × (n2/n1) × RCS1
where n2/n1 is the turns ratio of the current transformer.
The CS1 ADC should output a digital code equal to Vx/337 μV.
The CS1 gain trim register (Register 0x21) is adjusted until the
CS1 ADC value in Register 0x13 reads the correct digital code.
As described in the CS1 Pin section, the CS1 ADC has a
frequency response. To achieve more accurate trimming,
the following multiplication factor (M) should be used:
M = (−2 × 10−18 × fSW3) + (2 × 10−12 × fSW2) + (2 × 10−8 × fSW) + 0.9998
where fSW is the switching frequency of the power supply.
CS2 TRIM The CS2 trim must compensate for offset and gain errors. The
offset error requires both an analog trim and a digital trim. The
CS2 ADC range does not begin at 0 V but instead begins at
−25 mV to allow it to perform reverse current protection for the
OrFET circuit. Therefore, with −25 mV at the CS2 input, the ADC
code should read 0. With 0 mV at the CS2 input, the ADC code
should read 100 decimal. For this reason, the analog offset trim
is performed until the CS2 reading equals 100 decimal (not 0).
For this reason, also, the digital trim is required.
CS2 Offset Trim It is important to perform the CS2 offset trim as described in
the following steps.
1. Set the nominal full-scale sense resistor voltage drop in
Register 0x23, Bits[7:6].
2. Set high-side or low-side current sensing in Register 0x24,
Bit 7.
3. Offset errors can be introduced by the external bias
resistors and the internal current sources. Apply no-load
current across the sense resistor. Adjust the CS2 offset trim
value (Register 0x24, Bits[6:0]) until the CS2 value in
Register 0x18 reads as close to 100 decimal as possible.
4. Adjust the CS2 digital trim register (Register 0x25) until
the CS2 value in Register 0x18 reads 0.
The offset trim is now completed, and the ADC code reads 0 if
there is no-load current across the sense resistor.
CS2 Gain Trim After performing the offset trim, perform the gain trim to
remove any mismatch that is introduced by the sense resistor
tolerance. The ADP1043A can trim for sense resistors with a
tolerance of 1% or better.
1. Apply a known current (IOUT) across the sense resistor.
2. Adjust the CS2 gain trim value (Register 0x23, Bits[5:0])
until the CS2 value in Register 0x18 reads the value
calculated by the following formula:
CS2 Value = IOUT × 2457 × (RSENSE/FS)
where:
FS is the full-scale voltage drop.
RSENSE is the sense resistor value.
For example, if IOUT = 4.64 A, RSENSE = 20 mΩ, and
FS = 150 mV, then
CS2 Value = (4.64 A × 2457) × (20 mΩ/150 mV)
CS2 Value = 1520 decimal
The CS2 circuit is now trimmed. After the current sense trim is
performed, the OCP limits and settings should be configured.
VOLTAGE CALIBRATION AND TRIM The voltage sense inputs are optimized for sensing signals at
1 V and cannot sense a signal greater than 1.5 V. In a 12 V
system, a 12:1 resistor divider is required to reduce the 12 V
signal to below 1.5 V. It is recommended that the output voltage
of the power supply be reduced to 1 V for best performance.
The resistor divider can introduce errors, which need to be
trimmed. The ADP1043A has enough trim range to trim out
errors introduced by resistors with 0.5% tolerance or better.
The ADCs output a digital word of 2643 decimal (0xA53)
when there is exactly 1 V at their inputs.
OUTPUT VOLTAGE SETTING (VS3+, VS3− TRIM) The VS3 input requires a gain trim. Enable the power supply with
no-load current. The power supply output voltage is divided down
by the VS3 resistor divider to give 1 V at the VS3+ and VS3−
input pins. The VS3 trim register (Register 0x3A) is altered until
the VS3 value in Register 0x17 reads 2643 decimal (0xA53).
This step should be done before any other trim routines.
VS1 TRIM The VS1 input requires a gain trim. Enable the power supply with
no-load current. The VS1 voltage is divided down by the VS1
resistor divider to give 1 V at the VS1 pin. The VS1 trim register
(Register 0x38) is altered until the VS1 value in Register 0x15
reads 2643 decimal (0xA53).
VS2 TRIM The VS2 input requires a gain trim. Enable the power supply with
no-load current. The VS2 voltage is divided down by the VS2
resistor divider to give 1 V at the VS2 pin. The VS2 trim register
(Register 0x39) is altered until the VS2 value in Register 0x16
reads 2643 decimal (0xA53).
RTD/OTP TRIM A 100 kΩ NTC thermistor should be used with the ADP1043A.
In a PSU trim, the following procedure should be used:
1. Heat the thermistor or PSU to a known temperature that
will result in an OTP threshold.
2. Adjust the temperature gain trim register (Register 0x2B)
to give the correct temperature reading (Register 0x1A) at
this temperature.
3. Adjust the OTP threshold register (Register 0x2F) until the
OTP flag is set.
This procedure achieves the most accurate OTP, because it takes
into account the part-to-part variations of the ADP1043A and
the thermistor being used.
LAYOUT GUIDELINES This section explains best practices that should be followed to
ensure optimal performance of the ADP1043A. In general, all
components should be placed as close to the ADP1043A as
possible.
Several inputs to the ADP1043A are sensitive. Therefore, take
extra care when handling and soldering the part. Along with
correct cleaning of the IC after soldering, a short curing process
(1 hour at 150°C) is recommended. Analog Devices also recom-
mends encapsulating the IC in protective resin after this curing
to ensure that any impurities cannot contaminate the IC.
CS2 + and CS2− The routing of the traces from the sense resistor to the ADP1043A
should be laid out in parallel to each other. The traces should
also be kept close together and as far from the switch nodes as
possible.
VS3+ and VS3− The routing of the traces from the remote voltage sense point
to the ADP1043A should be laid out in parallel to each other.
The traces should also be kept close together and as far from
the switch nodes as possible.
VDD Place decoupling capacitors as close to the part as possible.
A 100 nF capacitor from VDD to AGND is recommended.
SDA and SCL The routing of the traces should be laid out in parallel to each
other. The traces should also be kept close together and as far
from the switch nodes as possible.
CS1 Run the traces from the current sense transformer to the
ADP1043A in parallel to each other. The traces should also be
kept close together and as far from the switch nodes as possible.
Exposed Pad The exposed pad underneath the ADP1043A should be
soldered to the PCB ground plane.
VCORE Place the 100 nF capacitor as close to the part as possible.
RES Place the 49.9 kΩ resistor as close to the part as possible.
RTD Route a single trace to the ADP1043A from the thermistor.
Place the thermistor close to the hottest part of the power supply.
AGND Create an AGND ground plane and make a single point (star)
connection to the power supply system ground.
ADP1043ACOMMUNICATION 2C INTERFACE Control of the ADP1043A is carried out via the I2C interface.
The ADP1043A is connected to the I2C bus as a slave device
under the control of a master device.
2C Address The I2C address of the ADP1043A is set by connecting an
external resistor from the ADD pin to AGND. Table 5 lists the
recommended resistor values and the associated I2C addresses.
Eight different addresses can be used. If an incorrect resistor
value is used and the resulting I2C address is close to a threshold
between two addresses, a flag is set (address flag in Register 0x03,
Bit 5; see Table 11).
The recommended values in Table 5 can vary by ±2 kΩ; the
ADP1043A still reports the same address. Therefore, it is recom-
mended that 1% tolerance resistors be used on the ADD pin. 2C Address 0x58 is the broadcast address, which allows multiple
parts to be written to simultaneously. By using the broadcast
address instead of a specific I2C address from Table 5, all
ADP1043A devices on the I2C bus are written to. The broadcast
address can be used for write commands only.
Table 5. Recommended Resistor Values for I2C Addresses
General I2C Timing The ADP1043A has a timeout feature to protect against a fault
condition on the SDA line. The I2C interface monitors the SDA
line and, if it stays low for time 0.65 ms < t_low < 1.3 ms, the 2C interface is reset and waits for another start condition.
The I2C specification defines specific conditions for different
types of read and write operations. General I2C read and write
operations are shown in the timing diagrams of Figure 32,
Figure 33, and Figure 34, and are described in this section.
The general I2C protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains high.
This indicates that a data stream follows. All slave peri-
pherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a
7-bit slave address (MSB first) plus a R/W bit, which
determines the direction of the data transfer, that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
2. The peripheral whose address corresponds to the
transmitted address responds by pulling the data line low
during the low period before the ninth clock pulse, known
as the acknowledge bit, and holding it low during the high
period of this clock pulse. All other devices on the bus
remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit is a 0, the master
writes to the slave device. If the R/W bit is a 1, the master
reads from the slave device.
3. Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-
high transition when the clock is high may be interpreted
as a stop signal.
4. If the operation is a write operation, the first data byte after
the slave address is a command byte that tells the slave
device what to expect next. It may be an instruction, such
as telling the slave device to expect a block write, or it may
be a register address that tells the slave where subsequent
data is to be written.
5. Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before a read operation, it
may be necessary to first perform a write operation to tell
the slave what sort of read operation to expect and/or the
address from which data is to be read.
6. When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases
the SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge bit. The master takes the data
line low during the low period before the 10th clock pulse,
and then high during the 10th clock pulse to assert a stop
condition.
If several read or write operations must be performed in succes-
sion, the master can send a repeat start condition instead of a
stop condition to begin a new operation.
START BYMASTER
STOP BYMASTER
ACK. BYADP1043AACK. BYADP1043A
ACK. BYADP1043A9A4A3A2A1A0R/WD7D6D5D4D3D2D1D0
SCL
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3DATA BYTE
SDA (CONTINUED)
SCL (CONTINUED)1D6D5D4D3D2D1D0Figure 32. Writing a Register Address to the Address Pointer Register, and Then Writing Data to the Selected Register
STOP BYMASTERACK. BYADP1043AACK. BYADP1043ASTART BYMASTER
SCL
SDA9A5A4A3A2A1A0R/WD7D6D5D4D3D2D1D0
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTEFigure 33. Writing to the Address Pointer Register Only
STOP BYMASTERSTART BYMASTERACK. BYADP1043A NO ACK. BYADP1043A
R/W
SCL99
SDAA6A5A4A3A2A1A0D7D6D5D4D3D2D1D0
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
DATA BYTE FROM ADP1043AFigure 34. Reading Data from a Previously Selected Register
ADP1043AEEPROM The EEPROM is partitioned into two major blocks: the factory
block and the main block. The factory block contains 128 8-bit
bytes, and the main block contains 8k 8-bit bytes.
Factory Block The factory block is organized into 128 bytes. It is used to store
the original Analog Devices factory calibration and register
settings. The user cannot change these settings. The contents
of the factory block can be downloaded to the registers at any
time by writing 0x01 to Register 0x7B.
Main Block The main block is available to store data. It is partitioned into
16 pages; each page contains 512 bytes. The data on each page
is sorted into bytes organized in the form of eight rows and 64
columns (see Figure 35).
PAGE 0 TO PAGE 15ROW 0
ROW 1
ROW 2
ROW 3
ROW 4
ROW 5
ROW 6
ROW 7
COLUMN0COLUMN1COLUMN2COLUMN62COLUMN63Figure 35. EEPROM Page Diagram
Main Block, Page 0 (User Settings) The ADP1043A user register settings are stored in Page 0 of the
main block. Every time that VDD is applied to the ADP1043A,
the register settings are automatically downloaded from Page 0
of the EEPROM to the registers. The ADP1043A has a unique
command to write new values to Page 0. This is done by writing
0x00 to Register 0x7B. Clicking the Update EEPROM button in
the Analog Devices software GUI also performs this task.
MAIN Block, Page 1 to Page 15 (Scratchpad) Page 1 to Page 15 of the main block can be used as a scratchpad
to store other data. Register 0x7C and Register 0x7D are used to
point to the page, row, and column of the byte to be accessed.
Write Example Write data 0xAA to Page 12, Row 3, Column 30 of the
ADP1043A at I2C Address 0x57.
Write: DevAddr=0x57 AddrPtr=0x7C Data=0x63 Write: DevAddr=0x57 AddrPtr=0x7D Data=0x1E Write: DevAddr=0x57 AddrPtr=0x7E Data=0xAA
Read Example Read data from Page 10, Row 7, Column 62 of the ADP1043A
at I2C Address 0x50.
Read: DevAddr=0x50 AddrPtr=0x7C Data=0x57 Read: DevAddr=0x50 AddrPtr=0x7D Data=0x3E Read: DevAddr=0x50 AddrPtr=0x7E
Table 6. EEPROM Registers Description Write the password to this register twice to unlock the EEPROM or to change its password
Write a command code to this register to perform one of the following EEPROM operations:
0x00: Upload registers to Page 0 of the main block (user settings)
0x01: Download factory settings (factory block) to the registers
0x02: Page erase operation Set XADR[6:0] of EEPROM:
XADR[6:3] selects one of 16 pages of the main block
XADR[2:0] selects one of eight rows per page Set YADR[5:0] of EEPROM:
YADR[5:0] selects one of 64 bytes in a single row Read or write to this register to read or program a byte in EEPROM main memory
EEPROM Password Lock The EEPROM password prevents the EEPROM contents from
being changed accidentally or purposely by an unwanted source.
The password ensures that critical specifications such as OVP
and OCP cannot be changed.
The EEPROM is always locked. When the EEPROM downloads
its contents to the registers, the password is also downloaded. If
the user writes the same password to Register 0x5E twice, the
EEPROM is unlocked and can be updated.
While the EEPROM is unlocked, it is possible to change the
password by writing a new value to Register 0x5E. After this
value is updated, the EEPROM contains the new password. The
factory default password is 0x00.
To update the EEPROM password, the user must write to
Register 0x7B. Writing 0x00 to this register updates the
EEPROM. The user must wait at least 50 ms after this write
command before attempting any further communication
with the ADP1043A.
Note that the EEPROM should not be written to for the first
500 ms after VDD has been applied.
EEPROM Password Change To change the EEPROM password, follow these steps:
1. Write the old password to Register 0x5E (password lock
register).
2. Write the new password to Register 0x5E (password lock
register) for the first time.
3. Write the new password to Register 0x5E (password lock
register) for the second time.
4. Write the new password to Register 0x5E (password lock
register) for the third time.
5. Write 0x00 to Register 0x7B.
6. Wait 50 ms.
7. To lock the EEPROM, write any value other than the
password value into Register 0x5E.
Cyclic Redundancy Check (CRC) The ADP1043A performs a check to ensure that the EEPROM
contents are correctly downloaded to registers at startup. It
compares the total number of 1s downloaded with the total
number of 1s that were last written to the EEPROM. If there is
a discrepancy, the CRC fault flag is set in Register 0x03, Bit 1.
This flag is used to ensure that the correct data is downloaded
from the EEPROM to the registers at startup.
SOFTWARE GUI A free software GUI is available for programming and configu-
ring the ADP1043A. The GUI is designed to be intuitive to
power supply designers and dramatically reduces power supply
design and development time. The software includes filter
design and power supply PWM topology windows. The GUI is
also an information center, displaying the status of all readings,
monitoring, and flags on the ADP1043A.
For more information about the GUI, contact Analog Devices
for the latest software and a user guide. Evaluation boards are
also available by contacting Analog Devices.
To download the latest GUI, click on the About button at the
top of the GUI Main screen. Click on the link to check for GUI
updates.
ADP1043AREGISTER LISTING
Table 7. Register List
Fault Registers
Value Registers
Current Sense and Current Limit Registers Name
Voltage Sense Registers VS3 voltage setting (remote voltage) VS1 overvoltage limit (OVP) VS2 and VS3 overvoltage limit (OVP) VS1 undervoltage limit (UVP) Line impedance limit Load line impedance VS1 trim VS2 trim VS3 trim Light load mode disable setting
ID Registers Silicon revision ID Manufacturer ID Device ID
PWM and Synchronous Rectification Timing Registers OUTAUX switching frequency setting PWM switching frequency setting OUTA rising edge timing (OUTA pin) OUTA rising edge setting (OUTA pin) OUTA falling edge timing (OUTA pin) OUTA falling edge setting (OUTA pin) OUTB rising edge timing (OUTB pin) OUTB rising edge setting (OUTB pin) OUTB falling edge timing (OUTB pin) OUTB falling edge setting (OUTB pin) OUTC rising edge timing (OUTC pin) OUTC rising edge setting (OUTC pin) OUTC falling edge timing (OUTC pin) OUTC falling edge setting (OUTC pin) OUTD rising edge timing (OUTD pin) OUTD rising edge setting (OUTD pin) OUTD falling edge timing (OUTD pin) OUTD falling edge setting (OUTD pin) SR1 rising edge timing (SR1 pin) SR1 rising edge setting (SR1 pin) SR1 falling edge timing (SR1 pin) SR1 falling edge setting (SR1 pin) SR2 rising edge timing (SR2 pin) SR2 rising edge setting (SR2 pin) SR2 falling edge timing (SR2 pin) SR2 falling edge setting (SR2 pin) OUTAUX rising edge timing (OUTAUX pin) OUTAUX rising edge setting (OUTAUX pin) OUTAUX falling edge timing (OUTAUX pin) OUTAUX falling edge setting (OUTAUX pin) OUTx and SRx pin disable setting Password lock
Digital Filter Programming Registers
Adaptive Dead Time Registers
EEPROM Registers ADP1043ADETAILED REGISTER DESCRIPTIONS
FAULT REGISTERS Register 0x04 to Register 0x07 are latched fault registers. In these registers, flags are not reset when the fault disappears. Flags are cleared
only by a register read (provided that the fault no longer persists). Note that latched bits are clocked on a low-to-high transition only. Also
note that these register bits are cleared when read via the I2C interface unless the fault is still present. It is recommended that the latched
fault register be read again after the faults disappear to ensure that the register is reset.
Table 8. Register 0x00—Fault Register 1 and Register 0x04—Latched Fault Register 1 (1 = Fault, 0 = Normal Operation)
Table 9. Register 0x01—Fault Register 2 and Register 0x05—Latched Fault Register 2 (1 = Fault, 0 = Normal Operation)
Table 10. Register 0x02—Fault Register 3 and Register 0x06—Latched Fault Register 3 (1 = Fault, 0 = Normal Operation)
Table 11. Register 0x03—Fault Register 4 and Register 0x07—Latched Fault Register 4 (1 = Fault, 0 = Normal Operation)
Table 12. Register 0x08 to Register 0x0D—Fault Configuration Registers Shutdown Debounce See Register 0x27 in Table 35 See Register 0x0E in Table 14 See Register 0x0E in Table 14 2 ms 2 ms 100 ms 100 ms 100 ms 100 ms 100 ms 100 ms 1 ms or 100 ms
Register 0x08 to Register 0x0D allow the user to program the response when each flag is set.
Table 13. Register 0x08 to Register 0x0D—Fault Configuration Register Bit Descriptions Description This bit specifies when the flag is set.
0 = after debounce.
1 = immediately. This bit specifies when the part is reenabled after the fault that triggered the flag has been resolved.
0 = reenable after the power supply reenable time set in Register 0x0E[1:0].
1 = remain disabled; power supply must be restarted to reenable.
