ADN4666 Fast Delivery |IC PHOENIX CO.,LIMITED

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ADN4666
3 V, LVDS, Quad CMOS Differential Line Receiver
3 V, LVDS, Quad CMOS
Differential Line ReceiverADN4666
FEATURES
±8 kV ESD IEC 61000-4-2 contact discharge on receiver input pins
400 Mbps (200 MHz) switching rates
100 ps channel-to-channel skew (typical)
100 ps differential skew (typical)
3.3 ns propagation delay (maximum)
3.3 V power supply
High impedance outputs on power-down
Low power design (10 mW quiescent typical)
Interoperable with existing 5 V LVDS drivers
Accepts small swing (350 mV typical) differential
input signal levels
Supports open, short, and terminated input fail-safe
Conforms to TIA/EIA-644 LVDS standard
Industrial operating temperature range of −40°C to +85°C
Available in surface-mount SOIC package and low profile
TSSOP package
APPLICATIONS
Point-to-point data transmission
Multidrop buses
Clock distribution networks
Backplane receivers
FUNCTIONAL BLOCK DIAGRAM
ROUT1
ROUT2
RIN1+
RIN1–
RIN2+
RIN2–
GND
Figure 1.
GENERAL DESCRIPTION
The ADN4666 is a quad-channel, CMOS low voltage differential
signaling (LVDS) line receiver offering data rates of over 400 Mbps
(200 MHz) and ultralow power consumption.
The device accepts low voltage (350 mV typical) differential
input signals and converts them to a single-ended, 3 V TTL/CMOS
logic level.
The ADN4666 also offers active high and active low enable/disable
inputs (EN and EN) that control all four receivers. These inputs
disable the receivers and switch the outputs to a high impedance
state. Consequently, the outputs of one or more ADN4666
devices can be multiplexed together to reduce the quiescent
power consumption to 10 mW typical.
The ADN4666 and its companion driver, the ADN4665, offer
a new solution to high speed, point-to-point data transmission
and offer a low power alternative to emitter-coupled logic (ECL)
or positive emitter-coupled logic (PECL).
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Theory of Operation .........................................................................9
Enable Inputs .................................................................................9
Applications Information .............................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
6/09—Revision 0: Initial Version
ADN4666SPECIFICATIONS
VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1, 2
Table 1. Test Conditions/Comments VCM = 1.2 V, 0.05 V, 2.95 V VCM = 1.2 V, 0.05 V, 2.95 V VID = 200 mV p-p VIN = 2.8 V, VCC = 3.6 V or 0 V VIN = 0 V, VCC = 3.6 V or 0 V VIN = 3.6 V, VCC = 0 V VIN = 0 V or VCC, other input = VCC or GND ICL = −18 mA IOH = −0.4 mA, VID = 200 mV IOH = −0.4 mA, input terminated IOH = −0.4 mA, input shorted IOL = 2 mA, VID = −200 mV Outputs enabled, VOUT = 0 V Outputs disabled, VOUT = 0 V or VCC EN and EN = VCC or GND, inputs open EN = GND and EN = VCC, inputs open IEC 61000-4-2 contact discharge Human body model Human body model Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified.
2 All typical values are given for VCC = 3.3 V and TA = 25°C. VCC is always higher than the RINx+ and RINx− voltage. RINx− and RINx+ have a voltage range of −0.2 V to VCC − VID/2. However, to be compliant with ac specifications, the
common-mode voltage range is 0.1 V to 2.3 V. VCMR is reduced for larger input differential voltage (VID). For example, if VID is 400 mV, VCMR is 0.2 V to 2.2 V. The fail-safe condition with inputs shorted is not supported
over the common-mode range of 0 V to 2.4 V, but is supported only with inputs shorted and no external common-mode voltage applied. VID up to VCC − 0 V can be
applied to the RINx+/RINx− inputs with the common-mode voltage set to VCC/2. Propagation delay and differential pulse skew decrease when VID is increased from 200 mV to
400 mV. Skew specifications apply for 200 mV ≤ VID ≤ 800 mV over the common-mode range. Output short-circuit current (IOS) is specified as magnitude only; a minus sign indicates direction only. Note that only one output should be shorted at a time; do not
exceed the maximum junction temperature specification (150°C).
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, CL = 15 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.1
Table 2.
RECEIVER
IS ENABLED Generator waveform for all tests, unless otherwise specified: f = 1 MHz, ZO = 50 Ω, tTLH and tTHL (0% to 100%) ≤ 3 ns for RINx+/RINx−.
2 AC parameters are guaranteed by design and characterization. All typical values are given for VCC = 3.3 V and TA = 25°C.
4 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground, unless otherwise specified. CL includes load and jig capacitance.
6 tSKD1 is the magnitude difference in the differential propagation delay time between the positive-going edge and the negative-going edge of the same channel. Channel-to-channel skew, tSKD2, is defined as the difference between the propagation delay of one channel and that of the others on the same chip with any event on
the inputs. tSKD3 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD3 specification applies to devices at the same VCC and within
5°C of each other within the operating temperature range. tSKD4 part-to-part skew is the differential channel-to-channel skew of any event between devices. The tSKD4 specification applies to devices over the recommended
operating temperature and voltage ranges and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay. fMAX generator input conditions: f = 200 MHz, tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, differential (1.05 V to 1.35 V p-p). fMAX generator output criteria: 60%/40%
duty cycle, VOL (maximum = 0.4 V), VOH (minimum = 2.7 V), and load = 15 pF (stray plus probes).
Test Circuits and Timing Diagrams
RINx+
RINx–
NOTES
1. CL=LOADAND TEST JIG CAPACITANCE.
ROUTx
50Ω50Ω
Figure 2. Test Circuit for Receiver Propagation Delay and Transition Time
ADN466680%80%
20%
1.5V
20%
1.5V
tPLHDtPHLD
RINx–
RINx+
0V (DIFFERENTIAL)
tTLH
VOH
VOL
1.2V
1.3V
1.1V
ROUTx
VID= 300mV p-p
Figure 3. Receiver Propagation Delay and Transition Time Waveforms
ROUTxRINx+
50Ω
RINx–
GND
NOTESCLINCLUDESLOADANDTESTJIGCAPACITANCE.S1CONNECTEDTOVCCFORtPZLANDtPLZMEASUREMENTS.S1CONNECTEDTO GNDFORtPZHANDtPHZMEASUREMENTS.
Figure 4. Test Circuit for Receiver Enable/Disable Delay
tPLZ
tPHZtPZH
tPZL
VOH
GND
VOL
VCCWITHEN= GND
OR OPENCIRCUITWITHEN=VCC
50%
50%
ROUTxWITHVID =–100mV
ROUTxWITHVID = +100mV
0.5V
1.5V
0.5V
1.5V
Figure 5. Receiver Enable/Disable Delay Waveforms
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION

Partno	Mfg	Dc	Qty	Available	Descript
ADN4666	AD	N/a	3	avai	3 V, LVDS, Quad CMOS Differential Line Receiver