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ADN2892ACPZ-500RL7
3.3 V 4.25 Gb/s Limiting Amplifier
3.3 V 4.25 Gb/s
Limiting Amplifier
Rev. PrA.
FEATURES
SFP reference design available
Input sensitivity: 3 mV p-p
65 ps rise/fall times
BW Select to support Multi-Rate 1x/2x/4x FC modules
Optional LOS Output Inversion to support SFF
CML outputs: 700 mV p-p differential
Programmable LOS detector: 3 mV to 45 mV
Rx signal strength indicator (RSSI):
SFF-8472 compliant average power measurement
Single supply operation: 3.3 V
Low power dissipation: 160 mW
Available in space-saving 3 × 3 mm 16-lead LFCSP
Increased Temperature Range: -40oC to 95oC
APPLICATIONS
SFP/SFF/GBIC optical transceivers
1x/2x/4x Multi-rate Fibre Channel receivers
LX4
WDM transponders
PRODUCT OVERVIEW The ADN2892 is a high gain, limiting amplifier optimized for
use in Fibre Channel and GbE optical receivers. The ADN2892
accepts input levels of up to 2.0 V p-p differential and has 3 mV
p-p differential input sensitivity. The ADN2892 provides the
receiver functions of quantization and loss of signal (LOS)
detection.
The ADN2892 has an on-chip selectable filter to reduce the BW
of the limamp to 1.5GHz in order to filter out the relaxation
oscillation of legacy 1Gb/s Fiber Channel transmitters with CD
lasers. The reduced BW will also allow for more optical Rx
sensitivity margin at the lower data rates such as 1xFC and
1GbE in multi-rate modules.
The limiting amplifier also measures average received power
based on a direct measurement of the photodiode current with
better than 1 dB of accuracy over the entire input range of the
receiver. This eliminates the need for external average Rx power
detection circuitry in SFF-8472 compliant optical transceivers.
The ADN2892 limiting amplifier operates from a single 3.3 V
supply, has low power dissipation, and is available in a space-
saving 3 × 3 mm 16-lead lead frame chip scale package
(LFCSP).
FUNCTIONAL BLOCK DIAGRAM ADuC7020
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................5
Thermal Resistance......................................................................5
ESD Caution..................................................................................5
Pin Configuration and Function Descriptions.............................6
Typical Performance Characteristics.............................................7
Theory of Operation........................................................................8
LIMAMP.......................................................................................8
Loss of Signal (LOS) Detector.....................................................8
Received Signal Strength Indicator (RSSI)................................8
Squelch Mode................................................................................8
Applications Information.................................................................9
PCB Design Guidelines................................................................9
Outline Dimensions.......................................................................11
Ordering Guide..........................................................................11
REVISION HISTORY Revision A: Initial Version
SPECIFICATIONS VCC = VMIN to VMAX, VEE = 0 V, TA = TMIN to TMAX, BW_SEL = 1, unless otherwise noted.
Table 1.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE θJA is specified for 4-layer PCB with exposed paddle soldered
to GND.
Table 3.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DRVCC
OUTP
OUTN
DRVEE
AVCC
PIN
NIN
AVEE
PD_CA
HODE
PD_VCCRSSI_OUTSQ
UELCH
THRADJ
BW_SEL
LOS_INV
LOS
Figure 2. Pin Configuration
Note: There is an exposed pad on the bottom of the package that must be connected to the GND plane with filled vias.
Table 4. Pin Function Descriptions
