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ADN2870ACPZADN/a244avai3.3 V, Dual Loop, 50 Mbps to 3.3 Gbps Laser Diode Driver


ADN2870ACPZ ,3.3 V, Dual Loop, 50 Mbps to 3.3 Gbps Laser Diode DriverAPPLICATIONS to make a complete SFP/SFF transceiver solution. An SFP Multirate OC3 to OC48-FEC SFP/ ..
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ADN2870ACPZ
3.3 V, Dual Loop, 50 Mbps to 3.3 Gbps Laser Diode Driver
3.3 V Dual-Loop, 50 Mbps to 3.3 Gbps
Laser Diode Driver

Rev. 0
FEATURES
SFP/SFF and SFF-8472 MSA-compliant
SFP reference design available
50 Mbps to 3.3 Gbps operation
Multirate 155 Mbps to 3.3 Gbps operation
Dual-loop control of average power and extinction ratio
Typical rise/fall time 60 ps
Bias current range 2 mA to 100 mA
Modulation current range 5 mA to 90 mA
Laser fail alarm and automatic laser shutdown (ALS)
Bias and modulation current monitoring
3.3 V operation
4 mm × 4 mm LFCSP package
Voltage setpoint control
Resistor setpoint control
APPLICATIONS
Multirate OC3 to OC48-FEC SFP/SFF modules
1×/2×/4× Fibre channel SFP/SFF modules
LX-4 modules
DWDM/CWDM SFP modules
1GE SFP/SFF transceiver modules
GENERAL DESCRIPTION

The ADN2870 laser diode driver is designed for advanced SFP
and SFF modules, using SFF-8472 digital diagnostics. The device
features dual-loop control of the average power and extinction
ratio, which automatically compensates for variations in laser
characteristics over temperature and aging. The laser need only
be calibrated at 25°C, eliminating the need for expensive and
time consuming temperature calibration. The ADN2870 supports
single-rate operation from 50 Mbps to 3.3 Gbps or multirate
from 155 Mbps to 3.3 Gbps.
Average power and extinction ratio can be set with a voltage
provided by a microcontroller DAC or by a trimmable resistor.
The part provides bias and modulation current monitoring as
well as fail alarms and automatic laser shutdown. The device
interfaces easily with the ADI ADuC70xx family of micro-
converters and with the ADN289x family of limiting amplifiers
to make a complete SFP/SFF transceiver solution. An SFP
reference design is available. The product is available in a space-
saving 4 mm ×4 mm LFCSP package specified over the −40°C to
+85°C temperature range.
Tx_FAIL
VCC
VCCVCC
GNDGND
VCC
Figure 1. Application Diagram Showing Microcontroller Interface
Protected by US patent: US6414974
TABLE OF CONTENTS
Specifications.....................................................................................3
SFP Timing Specifications...............................................................5
Absolute Maximum Ratings............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Typical Operating Characteristics..................................................8
Optical Waveforms Showing Multirate Performance Using
Low Cost Fabry Perot Tosa NEC NX7315UA..........................8
Optical Waveforms Showing Dual-Loop Performance Over
Temperature Using DFB Tosa SUMITOMO SLT2486............8
Performance Characteristics.......................................................9
Theory of Operation......................................................................11
Dual-Loop Control....................................................................11
Control.........................................................................................12
Voltage Setpoint Calibration.....................................................12
Resistor Setpoint Calibration....................................................14
IMPD Monitoring......................................................................14
Loop Bandwidth Selection........................................................15
Power Consumption..................................................................15
Automatic Laser Shutdown (TX_Disable)..............................15
Bias and Modulation Monitor Currents..................................15
Data Inputs..................................................................................15
Laser Diode Interfacing.............................................................16
Alarms..........................................................................................17
Outline Dimensions.......................................................................18
Ordering Guide..........................................................................18
REVISION HISTORY
8/04—Revision 0: Initial Version

SPECIFICATIONS
VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX,1 unless otherwise noted. Typical values as specified at 25°C.
Table 1.

1 Temperature range: –40°C to +85°C. Measured into a 15 Ω load (22 Ω resistor in parallel with digital scope 50 Ω input) using a 11110000 pattern at 2.5 Gbps, shown in Figure 2.
3 Guaranteed by design and characterization. Not production tested. When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
5 Guaranteed by design. Not production tested. IBIAS/IBMON ratio stability is defined in SFF-8472 revision 9 over temperature and supply variation.
7 ICC min for power calculation in the Power Consumption section. All VCC pins should be shorted together.
TO HIGH SPEEDDIGITALOSCILLOSCOPE50Ω INPUT
Figure 2. High Speed Electrical Test Output Circuit
SFP TIMING SPECIFICATIONS
Table 2.

Guaranteed by design and characterization. Not production tested.
DATAP
DATAN
DATAP–DATAN
Figure 3. Signal Level Definition
04510-0030.1µF10µF
1µH
3.3V
SFP HOST BOARD

Figure 4. Recommended SFP Supply
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.

___________________ Power consumption equations are provided in the Power Consumption
section. θJA is defined when part is soldered on a 4-layer board.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
FAILIB
MON
RRE
IMMONER
SET
CCBI
VSET
GND
VCC
IMODP
IMODN
GND
IBIAS
ALS
DATAN
DATAP
GND
PAVCAP
ERCAP
Figure 5. Pin Configuration
Table 4. Pin Fuction Descriptions

Note: The LFCSP package has an exposed paddle that must be connected to ground.
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3 V and TA = 25°C, unless otherwise noted.
OPTICAL WAVEFORMS SHOWING MULTIRATE
PERFORMANCE USING LOW COST FABRY PEROT TOSA
NEC NX7315UA

Note: No change to PAVCAP and ERCAP values
(ACQ LIMIT TEST) WAVEFORMS 1000

04510-016
Figure 6. Optical Eye 2.488 Gbps,65 ps/div, PRBS 231-1
PAV = −4.5 dBm, ER = 9 dB, Mask Margin 25%
(ACQ LIMIT TEST) WAVEFORMS 1000

04510-017
Figure 7. Optical Eye 622 Mbps, 264 ps/div, PRBS 231-1
PAV = −4.5 dBm, ER = 9 dB, Mask Margin 50%
(ACQ LIMIT TEST) WAVEFORMS 1000

04510-020
OPTICAL WAVEFORMS SHOWING DUAL-LOOP
PERFORMANCE OVER TEMPERATURE USING DFB TOSA
SUMITOMO SLT2486
(ACQ LIMIT TEST) WAVEFORMS 1001

04510-047
Figure 9. Optical Eye 2.488 Gbps, 65 ps/div, PRBS 231-1
PAV = 0 dBm, ER = 9 dB, Mask Margin 22%, TA = 25°C
(ACQ LIMIT TEST) WAVEFORMS 1001

04510-048
Figure 10. Optical Eye 2.488 Gbps, 65 ps/div, PRBS 231-1
PAV = −0.2 dBm, ER = 8.96 dB, Mask Margin 21%, TA = 85°C
PERFORMANCE CHARACTERISTICS
040802060100

MODULATION CURRENT (mA)
ISE TIM
Figure 11. Rise Time vs. Modulation Current, Ibias = 20 mA
040802060100

MODULATION CURRENT (mA)
FALL TIME (ps)
Figure 12. Fall Time vs. Modulation Current, Ibias = 20 mA 408060100
MODULATION CURRENT (mA)
RMINIS
TIC J
ITTE
R (ps
Figure 13. Deterministic Jitter vs. Modulation Current, Ibias = 20 mA
0.2204060801

MODULATION CURRENT (mA)
JITTER (rms)
Figure 14. Random Jitter vs. Modulation Current, Ibias = 20 mA
100204060801

MODULATION CURRENT (mA)
TOTAL S
CURRE
NT (mA)
Figure 15. Total Supply Current vs. Modulation Current
Total Supply Current = ICC + Ibias + Imod
–50–30–101030507090110

TEMPERATURE (°C)
CURRE
NT (mA)
Figure 16. Supply Current (ICC) vs. Temperature with ALS Asserted,
Ibias = 20 mA
–50–30–101030507090110
TEMPERATURE (°C)
IBIAS/IBM
N RATIO
Figure 17. IBIAS/IBMON Gain vs. Temperature, Ibias = 20 mA
Figure 18. ALS Assert Time, 5 µs/div
Figure 19. ALS Negate Time, 200 µs/div
–50–30–101030507090110

TEMPERATURE (°C)
OD/IM
N RATIO
Figure 20. IMOD/IMMON Gain vs. Temperature, Imod = 30 mA
Figure 21. FAIL Assert Time,1 µs/div
Figure 22. Time to Initialize, Including Reset, 40 ms/div
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