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ADN2819ACP-CML
Multi Rate Limiting Amplifier and Clock and Data Recovery ICs
Multirate to 2.7 Gb/s Clock and Data
Recovery IC with Integrated Limiting Amp
Rev. B
FEATURES
Meets SONET requirements for jitter
transfer/generation/tolerance
Quantizer sensitivity: 4 mV typical
Adjustable slice level: ±100 mV
1.9 GHz minimum bandwidth
Patented clock recovery architecture
Loss of signal detect range: 3 mV to 15 mV
Single reference clock frequency for all rates, including
15/14 (7%) wrapper rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK
LVPECL/LVDS/LVCMOS/LVTTL compatible inputs
(LVPECL/LVDS only at 155.52 MHz)
19.44 MHz oscillator on-chip to be used with external crystal
Loss of lock indicator
Loopback mode for high speed test data
Output squelch and bypass features
Single-supply operation: 3.3 V
Low power: 540 mW typical
7 mm × 7 mm 48-lead LFCSP
APPLICATIONS
SONET OC-3/-12/-48, SDH STM-1/-4/-16, GbE and 15/14
FEC rates
WDM transponders
Regenerators/repeaters
Test equipment
Backplane applications
PRODUCT DESCRIPTION The ADN2819 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at rates of OC-3,
OC-12, OC-48, Gigabit Ethernet, and 15/14 FEC rates. All
SONET jitter requirements are met, including jitter transfer,
jitter generation, and jitter tolerance. All specifications are
quoted for –40°C to +85°C ambient temperature, unless
otherwise noted.
The device is intended for WDM system applications, and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both native rates and 15/14 rate
digital wrappers are supported by the ADN2819, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at the
output.
The ADN2819 is available in a compact 7 mm × 7 mm, 48-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Pin Configuration and Function Descriptions.............................7
Definition of Terms..........................................................................9
Maximum, Minimum, and Typical Specifications...................9
Input Sensitivity and Input Overdrive.......................................9
Single-Ended vs. Differential......................................................9
LOS Response Time...................................................................10
Jitter Specifications.....................................................................10
Theory of Operation......................................................................12
Functional Description..................................................................14
Multirate Clock and Data Recovery.........................................14
Limiting Amplifier.....................................................................14
Slice Adjust..................................................................................14
Loss of Signal (LOS) Detector..................................................14
Reference Clock..........................................................................14
Lock Detector Operation..........................................................15
Squelch Mode.............................................................................16
Test Modes: Bypass and Loopback...........................................16
Applications Information..............................................................17
PCB Design Guidelines.............................................................17
Choosing AC-Coupling Capacitors.........................................19
DC-Coupled Application..........................................................20
LOL Toggling During Loss of Input Data...............................20
Outline Dimensions.......................................................................21
Ordering Guide..........................................................................21
REVISION HISTORY
5/04—Data Sheet Changed from Rev. A to Rev. B Updated Format..............................................................Universal
Changes to Specifications............................................................3
Changes to Table 7 and Table 8.................................................15
Updated Outline Dimensions...................................................21
Changes to Ordering Guide......................................................21
1/03—Data Sheet Changed from Rev. 0 to Rev. A Changes to Table IV...................................................................12
Updated OUTLINE DIMENSIONS........................................16
SPECIFICATIONS
Table 1. TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 µF, SLICEP = SLICEN = VCC, unless otherwise noted.
1 PIN and NIN should be differentially driven, ac-coupled for optimum sensitivity. PWD measurement made on quantizer outputs in bypass mode.
3 Jitter tolerance measurements are equipment limited. TDINP/N are CML inputs. If the drivers to the TDINP/N inputs are anything other than CML, they must be ac-coupled.
5 SEL0 and SEL1 have internal pull-down resistors, causing higher IIH.
ABSOLUTE MAXIMUM RATINGS
Table 2. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance 48-lead LFCSP, 4-layer board with exposed paddle soldered
to VCC
θJA = 25°C/W
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN1INDICATOR
TOPVIEW
ADN2819
THRADJ1VCC2VEE3
VREF4PIN5
NIN6
SLICEP7SLICEN8
VEE9LOL 10
XO1 11XO2 12
FCLKN 1
REFCLKP 14
FSEL 15
VEE 16
TDINP 17TDINN 1
VEE 19
CC 2
1 21
VEE 22
FSEL1 23
FSEL0 24
36VCC35VCC34VEE
33VEE32 SEL0
31 SEL1
30 SEL229VEE
28VCC27VEE
26VCC25 CF2
48 LOOPEN47
VEE
45 SD
44 B
VEE
VEE
CLK
UTP
CLK
UTN
39 SQ
DATAOUTP
DATAOUTN02999-B
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions CLKOUTP
DATAOUTP/NFigure 3. Output Timing
RESISTANCE (kΩ)Figure 4. LOS Comparator Trip Point Programming
02999-B
HYSTERESIS (dB)
FRE
NCYFigure 5. LOS Hysteresis OC-3, –40°C, 3.6 V, 23 – 1 PRBS Input Pattern, RTH = 90 kΩ
HYSTERESIS (dB)
FRE
NCYFigure 6. LOS Hysteresis OC-12, –40°C, 3.6 V, 23 – 1 PRBS Input Pattern, RTH = 90 kΩ
OUTP
OUTN
OUTP–OUTN02999-B
Figure 7. Single-Ended vs. Differential Output Specifications
DEFINITION OF TERMS
MAXIMUM, MINIMUM, AND TYPICAL
SPECIFICATIONS Specifications for every parameter are derived from statistical
analyses of data taken on multiple devices from multiple wafer
lots. Typical specifications are the mean of the distribution of
the data for that parameter. If a parameter has a maximum (or a
minimum), that value is calculated by adding to (or subtracting
from) the mean six times the standard deviation of the
distribution. This procedure is intended to tolerate production
variations. If the mean shifts by 1.5 standard deviations, the
remaining 4.5 standard deviations still provide a failure rate of
only 3.4 parts per million. For all tested parameters, the test
limits are guardbanded to account for tester variation and
therefore guarantee that no device is shipped outside of data
sheet specifications.
INPUT SENSITIVITY AND INPUT OVERDRIVE Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 8. For a sufficiently large positive input voltage,
the output is always Logic 1; similarly for negative inputs, the
output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this zone of confusion, the output may be either 1 or 0, or it may
even fail to attain a valid logic state. The width of this zone is
determined by the input voltage noise of the quantizer. The
center of the zone of confusion is the quantizer input offset
voltage. Input overdrive is the magnitude of signal required to
guarantee the correct logic level with 1 × 10–10 confidence level.
SENSITIVITY
(2× OVERDRIVE)02999-B
Figure 8. Input Sensitivity and Input Overdrive
SINGLE-ENDED VS. DIFFERENTIAL AC-coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~0.6 V. Driving the ADN2819 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 9 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values above and below the average value. It is
convenient to measure the peak-to-peak amplitude of this
signal and to call the minimum required value the quantizer
sensitivity. Referring to Figure 8, since both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive.
SCOPE
PROBE
10mV p-p02999-B
Figure 9. Single-Ended Sensitivity Measurement
PROBE
5mV p-p02999-B
Figure 10. Differential Sensitivity Measurement
Driving the ADN2819 differentially (see Figure 10), sensitivity
seems to improve by observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2819 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value since the other quantizer input is complementary to the
LOS RESPONSE TIME The LOS response time is the delay between the removal of the
input signal and indication of loss of signal (LOS) at SDOUT.
The ADN2819’s response time is 300 ns typ when the inputs are
dc-coupled. In practice, the time constant of ac-coupling at the
quantizer input determines the LOS response time.
JITTER SPECIFICATIONS The ADN2819 CDR is designed to achieve the best bit-error-
rate (BER) performance, and has exceeded the jitter transfer,
generation, and tolerance specifications proposed for
SONET/SDH equipment defined in the Telcordia Technologies
specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions measured in UI (unit
intervals), where 1 UI = 1 bit period. Jitter on the input data
can cause dynamic phase errors on the recovered clock
sampling edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections summarize the specifications of the jitter
generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level, and the
ADN2819 performance with respect to those specifications.
Jitter Generation Jitter generation specification limits the amount of jitter that
can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter has
a 12 kHz high-pass cutoff frequency, with a roll-off of
20 dB/decade and a low-pass cutoff frequency of at least
20 MHz. The jitter generated should be less than 0.01 UI rms
and 0.1 UI p-p.
Jitter Transfer Jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(see Figure 11).
JITTER FREQUENCY (kHz)
ITTE
R GAIN (dB)02999-B
Figure 11. Jitter Transfer Curve
Jitter Tolerance Jitter tolerance is defined as the peak-to-peak amplitude of the
sinusoidal jitter applied on the input signal that causes a 1 dB
power penalty. This is a stress test that is intended to ensure no
additional penalty is incurred under the operating conditions
(see Figure 12). Figure 13 shows the typical OC-48 jitter
tolerance performance of the ADN2819.
f1f2f3f4
JITTER FREQUENCY (Hz)
T J
ITTE
R AMP
UDE
(UI02999-B
Figure 12. SONET Jitter Tolerance Mask
0.1�
ITUDE
(UI02999-B
Figure 13. OC-48 Jitter Tolerance Curve
–8.510k100k1M100M
FREQUENCY (Hz)
10M
OC3_JIT_TOLERANCE
GBE_JIT_TOLERANCE
OC3_JIT_TRANSFER
GBE_JIT_TRANSFER
OC12_JIT_TOLERANCE
OC48_JIT_TOLERANCE
OC12_JIT_TRANSFER
OC48_JIT_TRANSFER02999-B
Figure 14. Jitter Transfer and Jitter Tracking BW
Table 4. Jitter Transfer and Tolerance: SONET Spec vs. ADN2819 Jitter tolerance measurements limited by test equipment capabilities.
THEORY OF OPERATION The ADN2819 is a delay-locked and phase-locked loop circuit
for clock recovery and data retiming from an NRZ encoded
data stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of the
input jitter. A separate phase control loop, comprised of the
VCO, tracks the low frequency components of the input jitter.
The initial frequency of the VCO is set by a third loop that
compares the VCO frequency with the reference frequency and
sets the coarse tuning voltage. The jitter tracking phase-locked
loop controls the VCO by the fine tuning control.
The delay- and phase-locked loops together track the phase of
the input data signal. For example, when the clock lags input
data, the phase detector drives the VCO to a higher frequency
and increases the delay through the phase shifter. Both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase while the delayed data
loses phase. Since the loop filter is an integrator, the static phase
error is driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for the frequency compensation of a second-
order phase-locked loop. This zero is placed in the feedback
path and therefore does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Since this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-locked loops together simultaneously
provide wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 15 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means the main PLL loop has low jitter peaking (see Figure 16),
which makes this circuit ideal for signal regenerator applica-
tions where jitter peaking in a cascade of regenerators can
contribute to hazardous jitter accumulation.
e(s)X(s)INPUTDATA
Z(s)
RECOVEREDCLOCK
o = VCO GAIN
psh = PHASE SHIFTER GAIN
JITTERTRANSFER FUNCTION
Z(s)
X(s)
s2 + s +1cn
n psh
TRACKING ERRORTRANSFER FUNCTION
e(s)
X(s)
s2 + s+do
d psh02999-B
Figure 15. PLL/DLL Architecture
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
since the jitter transfer function, Z(s)/X(s), provides the narrow-
band jitter filtering. See Table 4 for error transfer bandwidths
and jitter transfer bandwidths at the various data rates.
The delay-locked and phase-locked loops contribute to overall
jitter accommodation. At low frequencies of input jitter on the
data signal, the integrator in the loop filter provides high gain to
track large jitter amplitudes with small phase error. In this case,
the VCO is frequency modulated, and jitter is tracked as in an
ordinary phase-locked loop. The amount of low frequency jitter
that can be tracked is a function of the VCO tuning range. A
wider tuning range gives larger accommodation of low
frequency jitter. The internal loop control voltage remains small
for small phase errors, so the phase shifter remains close to the
center of its range, and therefore contributes little to the low
frequency jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track the input jitter. In this case,
the VCO control voltage becomes large and saturates, and the
VCO frequency dwells at one or the other extreme of its tuning
range. The size of the VCO tuning range therefore has only a
small effect on the jitter accommodation. The delay-locked loop
control voltage is now larger; thus, the phase shifter takes on the
burden of tracking the input jitter. The phase shifter range, in
UI, can be seen as a broad plateau on the jitter tolerance curve.
The phase shifter has a minimum range of 2 UI at all data rates.
