ADN2812ACP-RL7 ,Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting AmpAPPLICATIONS prevent chatter at the output. SONET OC-1/3/12/48 and all associated FEC rates The A ..
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AIVR3K42 , APLUS INTEGRATED CIRCUITS INC
AK002M4-31 , GaAs MMIC Control FET in SOT 143 DC-2.5 GHz
ADN2812ACP-RL7
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp
Continuous Rate 12.3 Mb/s to 2.7 Gb/s Clock and
Data Recovery IC with Integrated Limiting Amp
Rev. 0
FEATURES
Serial data input: 12.3 Mb/s to 2.7 Gb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 6 mV typical
Adjustable slice level: ±100 mV
Patented clock recovery architecture
Loss of signal (LOS) detect range: 3 mV to 15 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss of lock indicator 2C™ interface to access optional features
Single-supply operation: 3.3 V
Low power: 750 mW typical
5 mm × 5 mm 32-lead LFCSP
APPLICATIONS
SONET OC-1/3/12/48 and all associated FEC rates
Fibre Channel, 2× Fibre Channel , GbE, HDTV, etc.
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
PRODUCT DESCRIPTION The ADN2812 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2812 automati-
cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front end loss of signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2812 is available in a compact 5 mm × 5 mm 32-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM SLICEP/N
DATAOUTP/NLOSTHRADJCLKOUTP/N
VREF
Figure 1.
TABLE OF CONTENTS Specifications.....................................................................................3
Jitter Specifications.......................................................................4
Output and Timing Specifications.............................................5
Absolute Maximum Ratings............................................................6
Thermal Characteristics..............................................................6
ESD Caution..................................................................................6
Timing Characteristics.....................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics.............................................9 2C Interface Timing and Internal Register Description...........10
Terminology....................................................................................12
Jitter Specifications.........................................................................13
Jitter Generation.........................................................................13
Jitter Transfer...............................................................................13
Jitter Tolerance............................................................................13
Theory of Operation......................................................................14
Functional Description..................................................................16
Frequency Acquisition...............................................................16
Limiting Amplifier.....................................................................16
Slice Adjust..................................................................................16
Loss of Signal (LOS) Detector..................................................16
Lock Detector Operation..........................................................16
Harmonic Detector....................................................................17
Squelch Mode.............................................................................17
I2C Interface...............................................................................18
Reference Clock (Optional)......................................................18
Applications Information..............................................................21
PCB Design Guidelines.............................................................21
DC-Coupled Application..........................................................23
Coarse Data Rate Readback Look-Up Table...............................24
Outline Dimensions.......................................................................26
Ordering Guide..........................................................................26
REVISION HISTORY Revision 0: Initial Version
SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1. 1 PIN and NIN should be differentially driven and ac-coupled for optimum sensitivity.
JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 uF, SLICEP = SLICEN = VEE, Input Data Pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2. Jitter tolerance of the ADN2812 at these jitter frequencies is better than what the test equipment is able to measure.
OUTPUT AND TIMING SPECIFICATIONS
Table 3. Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed (see Table 6).
ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 µF,
SLICEP = SLICEN = VEE, unless otherwise noted.
Table 4. Stress above those listed under Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.
THERMAL CHARACTERISTICS
Thermal Resistance 32-LFCSP, 4-layer board with exposed paddle soldered to VEE
θJA = 28°C/W.
ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
TIMING CHARACTERISTICS CLKOUTP
DATAOUTP/N
Figure 2. Output Timing
OUTP
OUTN
OUTP–OUTN
Figure 3. Single-Ended vs. Differential Output Specifications
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TEST1 1
VCC 2
VREF 3
PIN1
INDICATOR
TOP VIEW(Not to Scale)
24 VCC
23 VEE
22 LOS
21 SDA
32 TEST2
20 SCK
19 SADDR5
18 VCC
17 VEE
THRADJ
9
REFCLKP 10
FCLKN 1
CC 1
VEE 13
2 14
1 15
LOL 16
NIN4
PIN5
SLICEP6
SLICEN7
VEE8
31 VC
30 VEE2
DATAOUTP
DATAOUTN
27 SQU
CLKOUTP
CLKOUTN
ADN2812*THERE IS AN EXPOSED PAD ON THE BOTTOM OFTHE PACKAGE THAT MUST BE CONNECTED TO GND.
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Type1 Description 1 TEST1 Connect to VCC.
2 VCC P Power for Limamp, LOS.
3 VREF AO Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
4 NIN AI Differential Data Input. CML.
5 PIN AI Differential Data Input. CML.
6 SLICEP AI Differential Slice Level Adjust Input. SLICEN AI Differential Slice Level Adjust Input. VEE P GND for Limamp, LOS. THRADJ AI LOS Threshold Setting Resistor.
10 REFCLKP DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
11 REFCLKN DI Differential REFCLK Input. 12.3 MHz to 200 MHz.
12 VCC P VCO Power.
13 VEE P VCO GND.
14 CF2 AO Frequency Loop Capacitor.
15 CF1 AO Frequency Loop Capacitor.
16 LOL DO Loss of Lock Indicator. LVTTL active high.
17 VEE P FLL Detector GND.
18 VCC P FLL Detector Power.
19 SADDR5 DI Slave Address Bit 5.
20 SCK DI I2C Clock Input.
21 SDA DI I2C Data Input.
22 LOS DO Loss of Signal Detect Output. Active high. LVTTL.
23 VEE P Output Buffer, I2C GND.
24 VCC P Output Buffer, I2C Power.
25 CLKOUTN DO Differential Recovered Clock Output. CML.
26 CLKOUTP DO Differential Recovered Clock Output. CML.
27 SQUELCH DI Disable Clock and Data Outputs. Active high. LVTLL.
28 DATAOUTN DO Differential Recovered Data Output. CML.
29 DATAOUTP DO Differential Recovered Data Output. CML.
30 VEE P Phase Detector, Phase Shifter GND.
31 VCC P Phase Detector, Phase Shifter Power.
32 TEST2 Connect to VCC.
Exposed Pad Pad P Connect to GND
TYPICAL PERFORMANCE CHARACTERISTICS RTH (Ω)10k100k
TRIP POINT (mV p-p)
Figure 5. LOS Comparator Trip Point Programming
1000101001k10k100k1M10M
JITTER FREQUENCY (Hz)
100M0.1
ITTE
R AMP
LITUDE
(UI)
Figure 6. Typical Measured Jitter Tolerance OC-48
2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION MSB = 1SET BYPIN 190 = WR1 = RD
SLAVE ADDRESS [6...0]R/WCTRL.
Figure 7. Slave Address Configuration
04228-0-006
Figure 8. I2C Write Data Transfer
S = START BITP = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVEA(M) = ACKNOWLEDGE BY MASTER
A(M) = LACK OF ACKNOWLEDGE BY MASTER
Figure 9. I2C Read Data Transfer
START BIT
STOP BITACKWRACK
SLADDR[4...0]
SLAVE ADDRESSSUB ADDRESSDATA
SUB ADDR[6...1]DATA[6...1]
SCK
SDA
Figure 10. I2C Data Transfer Timing
04228-0-009
SDA
SCK
tHD;DAT
tSU;DAT
tHIGHtSU;STAFigure 11. I2C Port Timing Diagram
Table 6. Internal Register Map1 1 All writeable registers default to 0x00.
Table 7. Miscellaneous Register, MISC
Table 8. Control Register, CTRLA1 Where DIV_FREF is the divided down reference referred to the 12.3 MHz to 25 MHz band (see the Reference Clock (Optional) section).
Table 9. Control Register, CTRLB
Table 10. Control Register, CTRLC
TERMINOLOGY
Input Sensitivity and Input Overdrive Sensitivity and overdrive specifications for the quantizer involve
offset voltage, gain, and noise. The relationship between the
logic output of the quantizer and the analog voltage input is
shown in Figure 12. For sufficiently large positive input voltage,
the output is always Logic 1 and, similarly for negative inputs,
the output is always Logic 0. However, the transitions between
output Logic Levels 1 and 0 are not at precisely defined input
voltage levels, but occur over a range of input voltages. Within
this range of input voltages, the output might be either 1 or 0, or
it might even fail to attain a valid logic state. The width of this
zone is determined by the input voltage noise of the quantizer.
The center of the zone is the quantizer input offset voltage.
Input overdrive is the magnitude of signal required to guarantee
the correct logic level with 1 × 10−10 confidence level.
OUTPUT(2× OVERDRIVE)
Figure 12. Input Sensitivity and Input Overdrive
Single-Ended vs. Differential AC coupling is typically used to drive the inputs to the
quantizer. The inputs are internally dc biased to a common-
mode potential of ~2.5 V. Driving the ADN2812 single-ended
and observing the quantizer input with an oscilloscope probe at
the point indicated in Figure 13 shows a binary signal with an
average value equal to the common-mode potential and
instantaneous values both above and below the average value. It
is convenient to measure the peak-to-peak amplitude of this
signal and call the minimum required value the quantizer
sensitivity. Referring to Figure 13, because both positive and
negative offsets need to be accommodated, the sensitivity is
twice the overdrive. The ADN2812 quantizer typically has
6 mV p-p sensitivity.
SCOPE
10mV p-p
VREF
Figure 13. Single-Ended Sensitivity Measurement
Driving the ADN2812 differentially (see Figure 14), sensitivity
seems to improve from observing the quantizer input with an
oscilloscope probe. This is an illusion caused by the use of a
single-ended probe. A 5 mV p-p signal appears to drive the
ADN2812 quantizer. However, the single-ended probe measures
only half the signal. The true quantizer input signal is twice this
value, because the other quantizer input is a complementary
signal to the signal being observed.
SCOPEPROBE
5mV p-p
VREF
5mV p-p
VREF
Figure 14. Differential Sensitivity Measurement
LOS Response Time LOS response time is the delay between removal of the input
signal and indication of loss of signal (LOS) at the LOS output,
Pin 22. When the inputs are dc-coupled, the LOS assert time of
the AD2812 is 500 ns typically and the de-assert time is 400 ns
typically,. In practice, the time constant produced by the ac
coupling at the quantizer input and the 50 Ω on-chip input
termination determines the LOS response time.
JITTER SPECIFICATIONS The ADN2812 CDR is designed to achieve the best bit-error-
rate (BER) performance and exceeds the jitter transfer, genera-
tion, and tolerance specifications proposed for SONET/SDH
equipment defined in the Telcordia Technologies specification.
Jitter is the dynamic displacement of digital signal edges from
their long-term average positions, measured in unit intervals
(UI), where 1 UI = 1 bit period. Jitter on the input data can
cause dynamic phase errors on the recovered clock sampling
edge. Jitter on the recovered clock causes jitter on the
retimed data.
The following sections briefly summarize the specifications of
jitter generation, transfer, and tolerance in accordance with the
Telcordia document (GR-253-CORE, Issue 3, September 2000)
for the optical interface at the equipment level and the
ADN2812 performance with respect to those specifications.
JITTER GENERATION The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input. For OC-48 devices, the band-pass filter
has a 12 kHz high-pass cutoff frequency with a roll-off of
20 dB/decade, and a low-pass cutoff frequency of at least
20 MHz. The jitter generated must be less than 0.01 UI rms, and
must be less than 0.1 UI p-p.
JITTER TRANSFER The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of the
jitter on an input signal that can be transferred to the output
signal (see Figure 15).
JITTER FREQUENCY (kHz)
JITTER GAIN (dB)
Figure 15. Jitter Transfer Curve
JITTER TOLERANCE The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal, which causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (see Figure 16).
0.15f1f2f3f4
JITTER FREQUENCY (kHz)
INPUT JITTER AMPLITUDE (UI p-p)
Figure 16. SONET Jitter Tolerance Mask
THEORY OF OPERATION The ADN2812 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops, which share a common control voltage.
A high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
controls the VCO by the fine-tuning control.
The delay- and phase-loops together track the phase of the
input data signal. For example, when the clock lags input data,
the phase detector drives the VCO to higher frequency, and also
increases the delay through the phase shifter; both these actions
serve to reduce the phase error between the clock and data. The
faster clock picks up phase, while the delayed data loses phase.
Because the loop filter is an integrator, the static phase error is
driven to zero.
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-
order phase-locked loop, and this zero is placed in the feedback
path and, thus, does not appear in the closed-loop transfer
function. Jitter peaking in a conventional second-order phase-
locked loop is caused by the presence of this zero in the closed-
loop transfer function. Because this circuit has no zero in the
closed-loop transfer, jitter peaking is minimized.
The delay- and phase-loops together simultaneously provide
wide-band jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 17 shows that
the jitter transfer function, Z(s)/X(s), is a second-order low-pass
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL loop has virtually zero jitter peaking
(see Figure 18). This makes this circuit ideal for signal regen-
erator applications, where jitter peaking in a cascade of
regenerators can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wide-band jitter accommodation,
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
X(s)
Z(s)RECOVEREDCLOCKINPUTDATA
d = PHASE DETECTOR GAINo = VCO GAINc = LOOP INTEGRATORpsh = PHASE SHIFTER GAINn = DIVIDE RATIO1s2+n pshs+ 1
Z(s)
X(s)
JITTER TRANSFER FUNCTIONs2d pshs++do
e(s)
X(s)
TRACKING ERROR TRANSFER FUNCTION
Figure 17. ADN2812 PLL/DLL Architecture
04228-0-016
FREQUENCY (kHz)
JITTER PEAKINGIN ORDINARY PLL
JITTER GAIN (n pshd pshcFigure 18. ADN2812 Jitter Response vs. Conventional PLL
The delay- and phase-loops contribute to overall jitter accom-
modation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors, so the phase shifter remains close to the center of
its range and thus contributes little to the low frequency jitter
accommodation.
